Micron Technology Incorporated

Bryce D Cook

John David Porter

Jeffrey P Wright

Donald M Morgan

Sean Stephen Eilert

Jaime Cummins

Kenneth Marion Curewitz

Nick Labrum

A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.

Multi-modal memory apparatuses and systems

Methods, apparatuses and systems related to protecting an apparatus against unauthorized accesses or usages are described. The apparatus may include a data protection circuit that protects an operating state of the apparatus, data stored in the apparatus, or a combination thereof when a temperature of the apparatus is outside of an operating range thereof.

Apparatus with power-based data protection mechanism and methods for operating the same

Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.

Address obfuscation for memory

Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain boundary along the output paths that generate the differential signal is staggered, such that the boundary occurs at an odd numbered stage in one differential output path and at an even numbered stage in the other differential output. Defining the power supply domain boundary in this manner can help ensure that the same logical state is present at the boundary in either of the differential output paths. This same logic signal should affect subsequent stages similarly from a speed perspective, and so should similarly affect the differential signals generated by each of the output paths. This means, among other things, that the differential signal as generated should tend to cross nearer to a midpoint voltage, which increases its compliance with certain integrated circuit specifications such as the Vox specification used for the differential data strobe in an SDRAM.

Circuitry and methods for improving differential signals that cross power domains

One or more embodiments of the present invention reduce uneven degradation during testing by providing for a toggling signal to be applied to remaining input paths which do not receive test signals. Therefore, rather than being held in a fixed state during the burn-in process, the remaining inputs are toggled as well. Consequently, they degrade at a more similar rate as their counterpart inputs that did receive test signals.

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Boise, ID, United States of America

Bryce D Cook