Intel Corporation

Bryant E Bigbee

Hong Wang

Gautham N Chinya

Baiju V Patel

Shivnandan D Kaushik

Xiang Chris Zou

Richard A Hankins

Prashant Sethi

John Thomas Shen

Per H Hammarlund

James Paul Held

John L Reid

Dion Rodgers

Anil Aggarwal

Chris J Newburn

Scott Dion Rodgers

Ittai Anati

John P Shen

Jason W Brandt

Xinmin Tian

Trung Am Diep

Francis X Mckeen

James B Crossland

Lawrence O Smith

Michael Cornaby

Robert Geva

Benjamin C Chaffin

Robert P Knight

Shiv Kaushik

Vincent J Zimmer

Hong Jiang

Raanan Sade

Gad Shlomo Sheaffer

Shreekant S Thakkar

Ron Gabor

Joseph Nuzman

Shahrokh Shahidzadeh

Andrew J Fish

Mark Doran

Yuval Yosef

Tomer Stark

Sanjiv M Shah

Ryan N Rakvic

Yoav Talgam

Gilbert A Neiger

Edward Thomas Grochowski

Milind Baburao Girkar

Quinn Able Jacobson

Michael Mishaeli

Asit K Mallick

Lance E Hacking

Frank Binns

Paul M Petersen

Ed Grochowski

Don Alan Van Dyke

Anil Aggawal

Will Deutsch

Muhammad Faisal Azeem

Eliezer Weissmann

Andrew J Herdrich

Alon Naveh

Dheeraj R Subbareddy

Eugene Gorbatov

Stephen Anthony Fischer

David B Papworth

Russell Jerome Fenger

Darrell D Boggs

David A Koufaty

Patrice L Roussel

Ganapati Srinivasa

Robert P Colwell

Douglas M Carmean

Doron Orenstein

Andrew D Henroid

Thomas R Huff

Scott D Hahn

Paolo L Narvaez

Rajesh R Shah

Gaurav Khanna

Mishali Naik

James Charles Abel

Paul Brett

Larry O Smith

David K Poulsen

Abirami Prabhakaran

William C Alexander, Iii

Jim B Crossland

Shivanandan Kaushik

Kenneth S Reneris

Rajesh R Sha

Chiv Kaushik

Millind Girkar

Tian Xinmin

Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

Hardware apparatuses and methods for memory corruption detection

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

In one embodiment, the present invention includes a method to establish a secure pre-boot environment in a computer system and performs at least one secure operation in the secure environment. In one embodiment, the secure operation may be storage of a secret in the secure pre-boot environment.

Providing a secure execution mode in a pre-boot environment

Mechanism for instruction set based thread execution of a plurality of instruction sequencers

Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

Apparatus, system, and method for persistent user-level thread

In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Hetergeneous processor apparatus and method

Method, apparatus and system embodiments to schedule OS-independent 'shreds' without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention

Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

System to profile and optimize user software in a managed run-time environment

Growing community of inventors

Scottsdale, AZ, United States of America

Bryant E Bigbee