Intel Corporation

Bryan R White

Balaji Vembu

David M Puffer

Altug Koker

Murali Ramadoss

Ankur N Shah

Aditya Navale

David J Cowperthwaite

Hema Chand Nalluri

Joydeep Ray

Mahesh S Natu

Abhishek R Appu

Changliang Wang

Niranjan L Cooray

Yunbiao Lin

Satyanantha Ramagopal Musunuri

Kritika Bala

Rajesh M Sankaran

Blaise B Fanning

Aravindh V Anantaraman

Brian K Langendorf

Michael Mishaeli

Aditya Sreenivas

Michael N Derr

Douglas Raymond Moran

Todd M Witter

Brent D Chartrand

Gustavo P Espinosa

Prashant D Chaudhari

Marc D Torrant

Nick G Eskandari

Daren J Schmidt

James Chapple

Sean T Baartmans

Neil Schaper

Cass A Blodgett

Tom E Dever

Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

Scalable I/O virtualization interrupt and scheduling

Apparatus and method for scalable error reporting. For example, one embodiment of an apparatus comprises error detection circuitry to detect an error in a component of a first tile within a tile-based hierarchy of a processing device; error classification circuitry to classify the error and record first error data based on the classification; a first tile interface to combine the first error data with second error data received from one or more other components associated with the first tile to generate first accumulated error data; and a master tile interface to combine the first accumulated error data with second accumulated error data received from at least one other tile interface to generate second accumulated error data and to provide the second accumulated error data to a host executing an application to process the second accumulated error data.

Apparatus and method for scalable error detection and reporting

An apparatus and method for managing pipes and planes within a virtual graphics processing engine. For example, one embodiment of a graphics processing apparatus comprises: a graphics processor comprising one or more display pipes to render one or more display planes, each of the one or more display pipes comprising a set of graphics processing hardware resources for executing graphics commands and rendering graphics images in the one or more display planes; and pipe and plane management hardware logic to manage pipe and plane assignment, the pipe and plane management hardware logic to associate a first virtual machine (VM) with one or more virtual display planes and to maintain a mapping between the one or more virtual display planes and at least one physical display plane.

Apparatus and method for display virtualization using mapping between virtual and physical display planes

An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.

Graphics engine partitioning mechanism

In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

System, apparatus and method for multi-die distributed memory mapped input/output support

An apparatus and method are described for fine grained sharing of graphics processing resources for example, one embodiment of a graphics processing apparatus comprises: a plurality of command buffers to store work elements from a plurality of virtual machines or applications, each work element indicating a command to be processed by graphics hardware and data identifying the virtual machine or application which generated the work element; a plurality of doorbell registers or memory regions, each doorbell register or memory region associated with a particular virtual machine or application, a virtual machine or application to store an indication in its doorbell register or memory region when it has stored a work element to a command buffer; and a work scheduler to read a work element from a command buffer responsive to detecting an indication in a doorbell register, the work scheduler to combine work elements from multiple virtual machines or applications in a submission to a graphics engine, the graphics engine to execute a work element using the data identifying a virtual machine or application associated with the work element, wherein different graphics engines are configured to simultaneously execute workloads belonging to different virtual machines or applications.

Efficient fine grained processing of graphics workloads in a virtualized environment

An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.

Memory mapped virtual doorbell mechanism

Various systems and methods for error handling are described herein. A system for error reporting and handling includes a common error handler that handles errors for a plurality of hardware devices, where the common error handler is operable with other parallel error reporting and handling mechanisms. The common error handler may be used to receive an error message from a hardware device, the error message related to an error; identify a source of the error message; identify a class of the error; identify an error definition of the error; determine whether the error requires a diagnostics operation as part of the error handling; initiate the diagnostics operation when the error requires the diagnostics operation; and clear the error at the hardware device.

Error reporting and handling using a common error handler

An apparatus and method for scalable interrupt reporting. For example, one embodiment of an apparatus comprises: a host processor to execute one or more processes having a corresponding one or more process contexts associated therewith; and a graphics processing engine to, upon initiating execution of a first process, determine a current process context associated with the first process including a first pointer to a first system memory region to store an interrupt status, a second pointer to a second system memory region to store interrupt enable and/or interrupt mask data for one or more interrupt events, and address/data values associated with a message signaled interrupt (MSI); the graphics processing engine, in response to an interrupt event, to evaluate the interrupt enable data from the second system memory region to determine whether the interrupt event is enabled, to report the interrupt event, if enabled, by writing a specified value to the first system memory region identified by the first pointer, and to generate a first MSI corresponding to the interrupt event by writing the MSI address/data values to an output accessible by the host processor.

Method and apparatus for a scalable interrupt infrastructure

Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a 'processor to processor' handoff or transaction.

Ordering mechanism for offload graphics scheduling

Growing community of inventors

Chandler, AZ, United States of America

Bryan R White