Advanced Micro Devices Corporation

Ati Technologies Ulc

Bryan P Broussard

Vydhyanathan Kalyanasundharam

Benjamin Tsien

Greggory D Donley

Eric Christopher Morton

Pravesh Gupta

Philip Ng

Anthony Asaro

Paul J Moyer

Kevin Michael Lepak

John P Petry

Richard Martin Born

Jimshed B Mirza

Michael J Tresidder

Maggie Chan

Ann M Ling

Vincent Cueva

Li Ou

Yaniv Adiri

Ivan Yanfeng Wang

Ganesh Balakrishnan

William Louie Walker

Amit P Apte

Chintan S Patel

Alan Dodson Smith

Gregg Donley

Girish Balaiah Aswathaiya

Samuel Abraham Lipson

Greggory Douglas Donley

The disclosed computer-implemented method includes interleaving a plurality of caches corresponding to a plurality of chiplets, identifying a source chiplet ID of a memory request of a new address for the interleaved caches, and storing, using an indexing scheme that incorporates the source chiplet ID, a shadow tag for a cache of the interleaved caches corresponding to the memory request. Various other methods, systems, and computer-readable media are also disclosed.

Shadow tag management for accelerator partitions

Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system includes multiple nodes. When power down negotiation is distributed, negotiation for system-wide power down occurs within a lower level of a node hierarchy prior to negotiation for power down occurring at a higher level of the node hierarchy. When power down negotiation is centralized, a given node combines a state of its clients with indications received on its downstream link and sends an indication on an upstream link based on the combining. Only a root node sends power down requests.

System-wide low power management

An exemplary data fabric device comprises a first traffic moderator configured to receive traffic destined for a specific endpoint accessible via a plurality of data paths and divert the traffic from a first data path included in the data paths to a second data path included in the data paths. The exemplary data fabric device also comprises a first interconnect controller that resides within the second data path and is configured to forward the traffic to the specific endpoint via a first communication link to test a functionality of the first communication link. Various other apparatuses, systems, and methods are also disclosed.

Apparatus, system, and method for conducting mission-mode testing on high-speed links

A system for combining write transactions of a large write includes a processor including at least a first die and a second die, and a link coupling the first die and the second die. When a link interface on one die transmits packets to the other die over the link, the link interface identifies, from a queue containing a plurality of write transactions, two or more write transactions in the queue that are candidates for combination based on one or more attributes of each write transaction. The link interface determines whether two or more candidate write transactions are combinable based on a set of conditions. When two or more candidate write transaction are combinable, the link interface combines the candidate write transactions into a single combined write transaction and transmits the combined write transaction. A link interface on the receiving die decodes the combined write transaction and iteratively regenerates the individual write transactions using control information in the combined write transaction.

Combining write transactions of a large write

A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.

Enhanced low-priority arbitration

Methods and systems are disclosed for cross-chiplet performance data streaming. Techniques disclosed include accumulating, by a subservient chiplet, event data associated with an event indicative of a performance aspect of the subservient chiplet; sending, by the subservient chiplet, the event data over a chiplet bus to a master chiplet; and adding, by the master chiplet, the received event data to an event record, the event record containing previously received, from the subservient chiplet over the chiplet bus, event data associated with the event.

Cross-chiplet performance data streaming

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple fabric interfaces in clients and a fabric. A packet transmitter in the fabric interface includes multiple queues, each for storing packets of a respective type, and a corresponding address history cache for each queue. Queue arbiters in the packet transmitter select candidate packets for issue and determine when address history caches on both sides of the link store the upper portion of the address. The packet transmitter sends a source identifier and a pointer for the request in the packet on the link, rather than the entire request address, which reduces the size of the packet. The queue arbiters support out-of-order issue from the queues. The queue arbiters detect conflicts with out-of-order issue and adjust the outbound packets and fields stored in the queue entries to avoid data corruption.

Method for maintaining cache consistency during reordering

A method of operating a processing unit includes storing a first copy of a first interrupt control value in a cache device of the processing unit, receiving from an interrupt controller a first interrupt message transmitted via an interconnect fabric, where the first interrupt message includes a second copy of the first interrupt control value, and if the first copy matches the second copy, servicing an interrupt specified in the first interrupt message.

Distributed interrupt priority and resolution of race conditions

Systems, apparatuses, and methods for reducing chiplet interrupt latency are disclosed. A system includes one or more processing nodes, one or more memory devices, a communication fabric coupled to the processing unit(s) and memory device(s) via link interfaces, and a power management unit. The power management unit manages the power states of the various components and the link interfaces of the system. If the power management unit detects a request to wake up a given component, and the link interface to the given component is powered down, then the power management unit sends an out-of-band signal to wake up the given component in parallel with powering up the link interface. Also, when multiple link interfaces need to be powered up, the power management unit powers up the multiple link interfaces in an order which complies with voltage regulator load-step requirements while minimizing the latency of pending operations.

Reducing chiplet wakeup latency

Systems, apparatuses, and methods for routing interrupts on a coherency probe network are disclosed. A computing system includes a plurality of processing nodes, a coherency probe network, and one or more control units. The coherency probe network carries coherency probe messages between coherent agents. Interrupts that are detected by a control unit are converted into messages that are compatible with coherency probe messages and then routed to a target destination via the coherency probe network. Interrupts are generated with a first encoding while coherency probe messages have a second encoding. Cache subsystems determine whether a message received via the coherency probe network is an interrupt message or a coherency probe message based on an encoding embedded in the received message. Interrupt messages are routed to interrupt controller(s) while coherency probe messages are processed in accordance with a coherence probe action field embedded in the message.

Probe interrupt delivery

Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system including multiple nodes utilizes a non-uniform memory access (NUMA) architecture. A first node receives a broadcast probe from a second node. The first node spoofs a miss response for a powered down third node, which prevents the third node from waking up to respond to the broadcast probe. Prior to powering down, the third node flushed its probe filter and caches, and updated its system memory with the received dirty cache lines. The computing system includes a master node for storing interrupt priorities of the multiple cores in the computing system for arbitrated interrupts. The cores store indications of fixed interrupt identifiers for each core in the computing system. Arbitrated and fixed interrupts are handled by cores with point-to-point unicast messages, rather than broadcast messages.

Multi-node system low power management

A computing system uses a memory for storing data, one or more clients for generating network traffic and a communication fabric with network switches. The network switches include centralized storage structures, rather than separate input and output storage structures. The network switches store particular metadata corresponding to received packets in a single, centralized collapsing queue where the age of the packets corresponds to a queue entry position. The payload data of the packets are stored in a separate memory, so the relatively large amount of data is not shifted during the lifetime of the packet in the network switch. The network switches select sparse queue entries in the collapsible queue, deallocate the selected queue entries, and shift remaining allocated queue entries toward a first end of the queue with a delay proportional to the radix of the network switches.

Growing community of inventors

Austin, TX, United States of America

Bryan P Broussard