Intel Corporation

Motorola Corporation

International Business Machines Corporation

Bryan P Black

Edward A Brekelbaum

Jeffrey P Rupley, Ii

Marvin A Denman

John P DeVale

Edward Thomas Grochowski

Ryan N Rakvic

Donald W McCauley

Youfeng Wu

Robert T Golla

Lee Evan Eisen

John Thomas Shen

Soummya Mallick

Seungyoon P Song

Albert J Loper, Jr

Russell A Reininger

Mohammed Hasan Taufique

Derwin Jallice

Gabriel H Loh

Hong Wang

Christopher B Wilkerson

Mauricio Breternitz, Jr

Perry H Wang

John P Shen

Jamison D Collins

Nicholas G Samra

Paul A Reed

M Clair Webb

Peter Sassone

Murali M Annavaram

Mark A Kearney

Bohuslav Rychlik

Wesley Attrot

Ralph M King

Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include 'conditional move' micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.

Micro-operation generator for deriving a plurality of single-destination micro-operations from a given predicated instruction

Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.

Multi-die processor

An apparatus including a first die including a plurality of conductive through substrate vias (TSVs); and a plurality of second dice each including a plurality of contact points coupled to the TSVs of the first die, the plurality of second dice arranged to collectively include a surface area approximating a surface area of the first die. A method including arranging a plurality of second dice on a first die such that collectively the plurality of second dice include a surface area approximating the surface area of the first die; and electrically coupling a plurality of second device to a plurality of the first die. A system including an electronic appliance including a printed circuit board and a module, the module including a first die including a plurality of TSVs; and the plurality of second dice arranged to collectively include a surface area approximating the surface area of the first die.

Method for incorporating existing silicon die into 3D integrated stack

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Memory array on more than one die

Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.

Prefetching from dynamic random access memory to a static random access memory

Implementation of a Bloom filter using multiple single-ported memory slices. A control value is combined with a hashed address value such that the resultant address value has the property that one, and only one, of the k memories or slices is selected for a given input value, a, for each bank. Collisions are thereby avoided and the multiple hash accesses for a given input value, a, may be performed concurrently. Other embodiments are also described and claimed.

Efficient Bloom filter

An apparatus and method are provided for renaming a logical register for which bit accesses of varying lengths are permitted, such as a predicate register. Rename logic supports renaming for both partial-bit accesses and bulk-bit accesses to bits of the register. Rename logic utilizes a rename map table associated with the logical register to be renamed and also includes a plurality of physical rename registers. They physical rename registers include a set of skinny physical rename registers to be used for renaming for partial-bit writes. The physical rename registers also include a set of fat physical rename registers to be used for renaming for bulk-bit writes. Additional sizes of physical rename registers may also be employed. The entries of the single physical rename map table may point to either fat or skinny physical rename registers.

Apparatus and method using different size rename registers for partial-bit and bulk-bit writes

A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.

Multi-purpose register cache

A method to handle data dependencies in a pipelined computer system is disclosed. The method includes allocating a plurality of registers, enabling execution of computer instructions concurrently by using the plurality of registers, and tracking and reducing data dependencies in the computer instructions by correlating a busy condition of a computer instruction to each register.

Predicate register file write by an instruction with a pending instruction having data dependency

A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.

Predictive filtering of register cache entry

A method and apparatus are provided for providing ready information to a scheduler. Dependence information is maintained in a relatively small map table, with potential loss of information when dependence information exceeds available space in the map table. Ready instructions are maintained, as space allows, in a select queue. Tags for scheduled instructions are maintained in a lookup queue, and dependency information for the scheduled instruction is maintained in an update queue, as space allows. Ready information for instructions in a scheduling window is updated based upon the information in the update queue. Loss of instruction information may occur, due to space limitations, at the map table, lookup queue, update queue, and/or select queue. Scheduling of lost instructions is handled by a lossy instruction handler.

Efficient instruction scheduling with lossy tracking of scheduling information

According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.

Cache mechanism

After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.

Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately

Speculative pre-computation and multithreading (SP), allows a processor to use spare hardware contexts to spawn speculative threads to very effectively pre-fetch data well in advance of the main thread. The burden of spawning threads may fall on the main thread via basic triggers. The speculative threads may also spawn other speculative threads via chaining triggers.

Growing community of inventors

Austin, TX, United States of America

Bryan P Black