Cirrus Logic Inc.

Telecruz Technology, Inc.

Wyse Technology Inc.

Bryan Michael Richter

Stephen A Smith

Dave M Singhal

Dayakar C Reddy

Daniel G Bezzant

Chester F Bassetti, Jr

Arunachalam Vaidyanathan

Suhas Anand Shetty

Kasturiraman Gopalaswamy

Abdul Q Kashmiri

Jerry L Clark

Ekaputra Laiman

Mike Assar

Kaushik L Popat

Chester F Bassetti

Jihad Y Abudayyeh

Kumar Satyanarayana Hebbalalu

A method for configuring a thin client connected to a communications network includes the thin client sending a request for a network address to an address server. The address server sends an assigned network address back to the thin client together with a location of a configuration server. The thin client sends a request for configuration information to the configuration server. The request for configuration information includes information on the thin client. The configuration server generates a configuration file containing configuration information based on the received thin client information. The configuration file is then sent by the configuration server to the thin client, which uses the configuration file for configuration.

Method and system for thin client configuration

A method and apparatus for maintaining the voltage level of data signals supplied to an integrated circuit, such as a PCMCIA card, at the same level as power also provided to the integrated circuit. Circuitry for maintaining the voltages at the same level is preferably embodied within a system having a card controller integrated circuit, a power supply, and a peripheral card socket for receiving a removable PCMCIA card. The power supply is controlled by the card controller to provide power to the PCMCIA card through the card socket at a voltage level matching internal voltage requirements of the PCMCIA card. The card controller is connected directly to the PCMCIA card by a signal transmission line. Circuitry is provided for ensuring that the voltage of data signals transmitted along the data bus line to the PCMCIA card substantially match the voltage of power provided from the power supply to the PCMCIA card along a power supply line. In this manner, damage resulting from a power mismatch within the PCMCIA card is avoided.

Computer system host adapter for controlling signal levels to peripheral

A method of recovering synchronization signals contained in a composite video signal. The synchronization signals are generally represented by voltage levels less than the blanking level of the video signal, and display data is represented by blanking level. A digital circuit controls a biasing circuit to generate a biasing voltage. A video signal is biased using the biasing voltage and the resulting biased video signal is provided as an input to an operational amplifier. A second input of the operational amplifier is driven by a reference voltage. The digital circuit monitors the output of the operational amplifier and controls the biasing voltage to cause the operational amplifier to clip the display data from the biased video signal and generate a signal representing synchronization signals.

Method and apparatus for accurately recovering the synchronization

A television system for displaying images having adjacent horizontal blocks with sharp contrast. In general, such sharp contrasts can cause the drive voltage (Hv) applied to an anode of a CRT display unit to change. The changes typically result in distortions in the displayed images. A correction logic is employed to regulate the voltage source that supplies the voltage to the anode of the CRT display unit. The correction logic examines the digital data representation of the images to determine the extent of contrast, and supplies a corresponding correction voltage to regulate the voltage source. Due to the correction voltage, a constant drive voltage is supplied to the anode. The distortions are thus minimized or eliminated.

Method and apparatus for displaying images having adjacent horizontal

A television system for recovering the digital data encoded in a television signal at an encoding frequency. The television signal is sampled at a frequency much higher than the encoding frequency, and the resulting sampled data elements are stored in a memory. Sampled data elements corresponding to a clock run-in portion (synchronization signal portion) of the television signal are examined to a samples interval equal to the number of samples per encoding clock periods. Transitions in the values of data elements are determined by examining consecutive sampled data elements. In general, sampled data elements are selected with an interval equal to the determined samples interval as representing the encoded digital data elements. However, the selection sequence is adjusted according to the transitions to ensure that the samples in only the stable portions of the television signal are selected.

Television system for recovering digital data encoded in a television

A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format. The system adapter may be included within a single interface expansion board which can be connected to the motherboard and CPU system bus or it can be directly connected or soldered to the motherboard and communicate with the socket controller and ATA hard disk drives using one or more busses.

Method and apparatus for interfacing between peripherals of multiple

An integrated circuit allows a user or system designer to program the length of a transaction cycle by programming the lengths of the setup time period, the command time period and the recovery time period, individually. An eight-bit register is used to store a two-bit prescaler value and a six-bit count value for each of the setup, command and recovery time periods. The value represented by the prescaler is then multiplied by the count value and the resulting value is input to a timer which counts down from the resulting value, signalling to a state machine when it has reached zero. A four-state state machine sends the command to begin each transaction cycle and each setup, command and recovery time period within each transaction cycle. The state machine is notified by the timer when the time period has elapsed for each of the three states so that it can send the signal to begin the next state. At the beginning of each command time period, the state machine also signals to the system that the command can be executed. At the beginning of each transaction cycle the state machine also sends the signal to load the next data value and address value from the first-in first-out stack onto the data and address busses, respectively.

Apparatus and method for programming the setup, command and recovery

A wired combinational logic arrangement responsive to N binary signal sources includes N circuits, one for each source. The circuits drive a common output terminal. Each circuit includes first and second devices for pulling the common terminal to first and second different voltages during successive abutting activation periods. The first device supplies a current to the common terminal that is considerably greater than the current supplied to the common terminal by the second device. The arrangement further includes a third device for pulling the common terminal to the second voltage at all times. The third device supplies a current to the common terminal that is either equal to or less than the current supplied by the second device.

Wired combinational logic circuit with pullup and pulldown devices

A low power clocking apparatus and method is used to reduce power consumption by an electronic system or an integrated circuit that is coupled to an external system via a system bus which is configured to selectively transmit or receive signals from the electronic system or integrated circuit. The electronic system or integrated circuit includes a plurality of sub-circuits. Each sub-circuit is configured to operate under control of a clock signal and further includes an apparatus for keeping or rejecting the clock signal. Once each sub-circuit within the electronic system or integrated circuit rejects the clock signal, an integral arbiter circuit disables the clock signal to all the sub-circuits. The arbiter circuit continuously monitors the system bus. Upon detecting that the sub-circuits will require the clock signal, the arbiter will re-enable the clock signal to all of the sub-circuits.

Low power clocking apparatus and method

The design and implementation of a low power CMOS bi-directional I/O buffer that translates low voltage core logic level signals into the highest logic level signals to drive the final output stage which outputs a selectable logic level signal. The buffer further translates input signals of a variety of logic levels into low voltage core logic level signals. In either case, AC and DC power consumption is minimized in a mixed power supply environment that requires voltage translation to represent the proper binary logic levels. An multivoltage I/O buffer having multiple input-receiving NOR gates is also described. The NOR gates of the multivoltage I/O buffer having triggering levels optimized for differing core voltage levels. Also described is a host adapted system for interfacing between and removable peripheral card and a host computer. The host adaptor includes an integrated circuit employing the multivoltage bi-directional I/O buffer.

Method and apparatus for controlling a mixed voltage interface in a

A method and apparatus for increasing the perceived gradation of the shades in visual displays is disclosed. A plurality of signals control the intensity of a sub-pixel of a display so that display can exhibit a native number of shades. Frame rate modulation techniques are used to increase the perceived gradation. Finally, flicker is reduced by spreading the phases of the modulating pixels across time, and the horizontal and vertical axes of the display.

Apparatus for shade gradation enhancement and flicker reduction in

The perception of grayscale shading on a digitally commanded display is produced by commanding pixels of the display with brightness-setting signals of differing average duty cycles. Brightness-setting signals having one brightness level associated with them are phase shifted in relation to time and distributed to spaced apart pixel locations at which the one brightness level is to be produced. The energization of spatially adjacent pixels is scattered in time and pixels which are energized at the same time are selected to be spatially scattered so as to avoid the perception of visual disturbances such as flickering and surface streaming.

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Fremont, CA, United States of America

Bryan Michael Richter