Advanced Micro Devices Corporation

Bryan M Tracy

Steven C Avanzino

Robin W Cheung

Ming-Ren Lin

Subhash Gupta

Scott D Luning

Darrell M Erb

Richard K Klein

Roger L Alvis

Janice Gray

Minh Van Ngo

Paul Raymond Besser

Paul J Steffan

Donald L Wollesen

Richard C Blish

Mehrdad Mahanpour

Ming Chun Chen

Andrew Norman Erickson

Jeremias D Romero

Ayesha R Kizchery

Mohammad Masoodi

A method and system for performing backside analysis on a silicon-on-insulator (SOI) device is disclosed. The SOI device includes a silicon layer, a buried oxide layer (BOX), an active layer containing active devices, and multiple metal layers. The method includes opening a window in the silicon layer using the BOX layer as a stop, and using the window as a field of view to view structures in the active layer with a microscope, wherein defects can be detected in the device without delayering any of the metal layers, such that the device remains functional for testing.

Method and system for performing failure analysis on a multilayer silicon-on-insulator (SOI) device

A method and system for performing failure analysis on a silicon on insulator (SOI) semiconductor device is disclosed. The SOI device includes a plurality of conductive structures in a silicon region. The silicon resides on a box insulator, which resides on a silicon substrate. The method and system include providing a cross-section of the SOI semiconductor device. The cross-section of the SOI semiconductor device includes a portion of the plurality of conductive structures. The method and system also include staining the cross-section of the SOI semiconductor device using a stain. The stain etches the silicon region in the SOI semiconductor device without etching a remaining portion of the SOI semiconductor device not composed of silicon.

Method and system for using TMAH for staining copper silicon on insulator semiconductor device cross sections

A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms first, which subsequently volumetrically contracts, thereby forming a titanium aluminide compound, with the contraction being absorbed by the aluminum. Because the alloy is reacted to form the metal compound prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced.

Method for reducing stress-induced voids for 0.25 &mgr;m micron and smaller semiconductor chip technology by annealing interconnect lines prior to ILD deposition and semiconductor chip made thereby

A semiconductor wafer optical scanning system and method for determining defects on a semiconductor wafer is disclosed. The method for determining wafer defects is based on maximum allowable defects on a swath basis, rather than maximum allowable defects on a wafer basis. The method step include determining the scanned area of an individual swath that is based on a recipe set-up, consistent with the capability of the optical scanning equipment being used and the particular semiconductor wafer being tested for defects. The predetermined swath area is supplied and stored in the optical scanning system along with the maximum allowable defect density determined by the user. By using the predetermined maximum allowable defects for a swath as a limit, defect analysis may be performed on the entire wafer. The optical scanning system would stop acquiring defects for the current swath being analyzed whenever the defect limit is reached, or until the swath defect analysis has been completed. The optical scanning would proceed to the next swath determining its defect and continuing in such a manner until the wafer is completely scanned.

Semiconductor wafer optical scanning system and method using swath-area

An ion implant process is disclosed for forming an amorphous structure in a semiconductor metallization barrier layer, which barrier may be a pure metal barrier, such as titanium, tantalum, tungsten, or metal compound barrier, such as titanium nitride, or titanium-tungsten. The implant is preferably an ion of the barrier metal being used, which is implanted such that an amorphous (texture-less non-crystalline) layer is produced. Other implant species, such as nitrogen or noble gases, such as neon or argon may also be used. Subsequent deposition of the interconnect metallization (typically Al or Cu) results in an interconnect metal structure having a high degree of texture which is characterized by a very narrow distribution of crystallographic orientations in the Al or Cu film. The highly textured Al or Cu metallization results in optimizing the interconnect metal for maximum electromigration performance. The implant energy is chosen such that the tail of the Gaussian distribution of ion's stopping distances extends above the top of the barrier metal film. The ion implantation forms a non-crystalline metal structure in the metal barrier film such that there is no crystalline metal to act as a 'seed' for nucleation during the metallization deposition and subsequent processing. Thus, the final interconnect metallization texture (Al or Cu) will not be governed by the texture of the underlying metal barrier layer which results in an optimized interconnect metal structure with maximum electromigration performance characteristics.

Apparatus and method to improve electromigration performance by use of

Electron beam emitting filaments having a tip with a radius of curvature less than about 50 .ANG. are produced using focused ion beam milling. In one embodiment, platinum is deposited on a tungsten loop electron beam filament and sharpened using focused ion beam milling to a radius of curvature less than about 50 .ANG..

Electron beam emitting tungsten filament

A method for navigating directly to defects on a blank wafer caused by particles dropped from process tools. A blank wafer is marked with fiducial marks, the number of initial defects on the blank wafer is determined and the position coordinates of the initial defects and the fiducial marks are recorded. The blank wafer is placed into a selected process tool and the additional defects that are caused by particles dropped from the process tool are detected in an inspection tool and their position coordinates are determined and recorded as well as the position coordinates of the fiducial marks. The blank wafer is then placed in an analysis tool that is able to navigate directly to each of the additional defects at a high magnification using the position coordinates of the fiducial marks.

Use of fiducial marks for improved blank wafer defect review

A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the reservoir from diffusing into the insulating layer. The barrier layer and reservoir may be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and reservoir may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Copper reservoir for reducing electromigration effects associated with a

Method of forming electron beam emitting tungsten filament

A diode is formed at the tip of a pointed portion of a probe of a scanning probe microscope. When the diode is forward biased, the current through the diode varies with the temperature of the diode. The magnitude of the current is an indication of the temperature of the tip of the probe. If the tip is scanned over a surface, a thermal map of the surface can be made and hot spots on the surface located. In some embodiments, the pointed portion of the probe is made of a semiconductor material (for example, silicon). A layer of a metal (for example, platinum) is made to contact the semiconductor material of the pointed portion only at the tip of the pointed portion, thereby forming a very small temperature sensing Schottky diode at the tip of the pointed portion.

Temperature sensing probe for microthermometry

A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Growing community of inventors

Oakland, CA, United States of America

Bryan M Tracy