International Business Machines Corporation

Bryan L Jackson

Dharmendra S Modha

Andrew S Cassidy

John Vernon Arthur

Paul A Merolla

Jun Sawada

Rodrigo Alvarez-Icaza Rivera

Subramanian Srikanteswara Iyer

Steven Kyle Esser

Filipp A Akopyan

John Edward Barth, Jr

Myron Dale Flickner

Benjamin G Shaw

Rodrigo Alvarez-Icaza

Norman Jerome Pass

Rodrigo Alvarez Icaza Rivera

Bipin Rajendran

Rathinakumar Appuswamy

John E Barth

David J Berg

Michael V DeBole

Embodiments of the invention provide a neurosynaptic network circuit comprising multiple neurosynaptic devices including a plurality of neurosynaptic core circuits for processing one or more data packets. The neurosynaptic devices further include a routing system for routing the data packets between the core circuits. At least one of the neurosynaptic devices is faulty. The routing system is configured for selectively bypassing each faulty neurosynaptic device when processing and routing the data packets.

Yield tolerance in a neurosynaptic system

In one general embodiment, a computer-implemented method is provided. The computer-implemented method includes receiving data comprising at least one data stream. Each data stream of the at least one data stream includes a plurality of points. The computer-implemented method also includes producing a result by remapping the at least one data stream in a point-by-point manner, and outputting the result.

Streaming programmable point mapper and compute hardware

The present invention provides a system comprising multiple core circuits. Each core circuit comprises multiple electronic axons for receiving event packets, multiple electronic neurons for generating event packets, and a fanout crossbar including multiple electronic synapse devices for interconnecting the neurons with the axons. The system further comprises a routing system for routing event packets between the core circuits. The routing system virtually connects each neuron with one or more programmable target axons for the neuron by routing each event packet generated by the neuron to the target axons. Each target axon for each neuron of each core circuit is an axon located on the same core circuit as, or a different core circuit than, the neuron.

Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network

A multiplexed neural core circuit according to one embodiment comprises, for an integer multiplexing factor T that is greater than zero, T sets of electronic neurons, T sets of electronic axons, where each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses that each interconnect a single electronic axon to a single electronic neuron, where the interconnection network interconnects each set of the T sets of electronic axons to its corresponding set of electronic neurons.

Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency

Embodiments of the invention provide a system and circuit interconnecting peripheral devices to neurosynaptic core circuits. The neurosynaptic system includes an interconnect that includes different types of communication channels. A device connects to the neurosynaptic system via the interconnect.

Peripheral device interconnections for neurosynaptic systems

One embodiment provides a system comprising a memory device for maintaining deterministic neural data relating to a digital neuron and a logic circuit for deterministic neural computation and stochastic neural computation. Deterministic neural computation comprises processing a neuronal state of the neuron based on the deterministic neural data maintained. Stochastic neural computation comprises generating stochastic neural data relating to the neuron and processing the neuronal state of the neuron based on the stochastic neural data generated.

Dual deterministic and stochastic neurosynaptic core circuit

Embodiments of the invention relate to implementing a probabilistic graphical model (PGM) using magnetic tunnel junctions (MTJs). One embodiment comprises a memory array of magnetic tunnel junctions and a driver unit for programming the memory array to represent a probabilistic graphical model. The magnetic tunnel junctions are organized into multiple subsets of magnetic tunnel junctions. The driver unit selectively applies an electrical pulse to a subset of magnetic tunnel junctions to program information representing a probabilistic belief state in said subset of magnetic tunnel junctions.

Implementing stochastic networks using magnetic tunnel junctions

Embodiments of the invention provide a system for scaling multi-core neurosynaptic networks. The system comprises multiple network circuits. Each network circuit comprises a plurality of neurosynaptic core circuits. Each core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of electronic synapse devices. An interconnect fabric couples the network circuits. Each network circuit has at least one network interface. Each network interface for each network circuit enables data exchange between the network circuit and another network circuit by tagging each data packet from the network circuit with corresponding routing information.

Scaling multi-core neurosynaptic networks across chip boundaries

One embodiment of the invention provides a system comprising at least one data-to-spike converter unit for converting input numeric data received by the system to spike event data. Each data-to-spike converter unit is configured to support one or more spike codes.

Converting digital numeric data to spike event data

One embodiment of the invention provides a system comprising at least one spike-to-data converter unit for converting spike event data generated by neurons to output numeric data. Each spike-to-data converter unit is configured to support one or more spike codes.

Converting spike event data to digital numeric data

Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.

Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

The present invention provides a system comprising a neurosynaptic processing device including multiple neurosynaptic core circuits for parallel processing, and a serial processing device including at least one processor core for serial processing. Each neurosynaptic core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of synapse devices. The system further comprises an interconnect circuit for coupling the neurosynaptic processing device with the serial processing device. The interconnect circuit enables the exchange of data packets between the neurosynaptic processing device and the serial processing device.

Coupling parallel event-driven computation with serial computation

Embodiments of the invention provide a neurosynaptic system comprising a delay unit for receiving and buffering axonal inputs, and a neural computation unit for generating neuronal outputs by performing a set of computations based on at least one axonal input received by the delay unit. The system further comprises a permutation unit for receiving external inputs to the system, and transmitting external outputs from the system. The permutation unit maps each external input received as either an axonal input to the delay unit or an external output from the system. The permutation unit maps each neuronal output generated by the neural computation unit as either an axonal input to the delay unit or an external output from the system. The neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the neurons with the axons.

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Fremont, CA, United States of America

Bryan L Jackson