International Business Machines Corporation

Bryan Keith Bullis

Darryl Jonathan Rumph

Timothy B Brodnax

Steven A King

Michael Steven Siegel

Dale A Rickard

William Robert Lee

Peter Michael Kogge

Robert Brian Likovich, Jr

Robert Glen Gerowitz

Daniel L Stanley

Raj Kumar Singh

Michael Patrick Muhlada

John Charles Goss

Robert L Schoenike

Foster Beaver White

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer, and input signals from an array and a clock line providing current time. Also included is a decision block that determines which of the searches are critical and which, during peak calendar search periods, can be postponed with minimal impact to the system. The postponed searches are then conducted at a time when there is available calendar search capacity.

Apparatus and method to coordinate calendar searches in a network scheduler given limited resources

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices, is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer and input signals from array and a clock line providing current time. The results of the search are loaded into a Winner Valid array and a Winner Location array. A final decision logic circuit parses information in the Winner Valid array and Winner Location array to generate a final Winner Valid Signal, the identity of the winning calendar and the winning location. Winning is used to define the status of the calendar in the calendar status array selected as a result of a search process being executed on a plurality of calendars in the calendar status array.

Coordination of calendar searches in a network scheduler

A system that indicates which frame should next be removed by a scheduler from flow queues within a network device, such as a router, network processor, and like devices is disclosed. The system includes a search engine that searches a set of calendars under the control of a Finite State Machine (FSM), a current pointer and input signals from array and a clock line providing current time. The results of the search are loaded into a Winner Valid array and a Winner Location array. A final decision logic circuit parses information in the Winner Valid array and Winner Location array to generate a final Winner Valid Signal, the identity of the winning calendar and the winning location. Winning is used to define the status of the calendar in the calendar status array that is selected as a result of a search process being executed on a plurality of calendars in the calendar status array.

Apparatus and method to coordinate calendar searches in a network scheduler

A method and system for providing simulation of an integrated circuit during development of the integrated circuit is disclosed. The integrated circuit has an island that includes an interface. The method and system include a snooper, a checker and a generator. The snooper is coupled with an interface and is for obtaining an output provided by the island during simulation. The checker is coupled with an interface and is for checking the output to determine whether the output is a desired output. The generator is coupled with an interface and is for providing an input to the interface during simulation. The generator is coupled with a test case that directs the generator.

Method and system for providing hierarchical self-checking in ASIC simulation

An improved asynchronous data buffer is disclosed. The data buffer comprises an entry section and a signaling circuit coupled to the entry section, the signaling circuit for signaling the data buffer to transfer a portion of a data cell from the entry section prior to the data cell being completely received by the entry section. Through the use of the data buffer in accordance with the present invention, data transfer systems are improved in two ways. Firsts by enabling data to be transferred before it is completely stored into the buffer, the latency that is typically required for data cell transfer is reduced. Second, the buffer storage space that is typically required to store a complete data cell is also reduced. This twofold improvement produces increased data transfer rates while decreasing the amount of required buffer storage space.

Asynchronous data buffer and a method of use thereof

Descriptive statements representative of a communication level coupling the functional logic of an integrated circuit to the external environment is translated into complex functional specification language for input to hardware design programs. Plain language within the functional specifications is converted to proper design language to implement hardware described by the functional specification.

Hardware design language generation for input/output logic level

Video data is decompressed in a coder/decoder (CODEC) and then scaled in a scaler device before being provided to a frame buffer within a display adapter of a data processing system. Since the scaling of the video data often results in a significant increase in the required bandwidth, a buffer implemented within the scaling device may reach a threshold level whereby it is not desired that any more scaled data be received before being transmitted to the frame buffer. When such a threshold level is reached, a stall signal is sent to the interface between the scaler device and the CODEC device providing the pixel data, which results in the stopping of the transmission of pixel data from the CODEC to the scaler device. Assertion of the stall signal results in the suspension of the transmission of the horizontal and vertical synchronization signals and the pixel clock signal from the scaler device to the CODEC device.

System and method for pacing the rate of display of decompressed video

A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.

Synchronizing a prediction RAM

A computer memory system having partitioned page address for instructions and operands. The partitioning scheme for the virtual addressing memory minimizes the delay between the translation logic and the page translation RAMs. Computer processor performance is delayed by only a single clock cycle by the sharing of the memory address bus control between two address processors.

Partitioning of virtual addressing memory

A data processing system includes branch prediction apparatus for storing branch data in a branch prediction RAM after each branch has occurred. The RAM interfaces with branch logic means which tracks whether a branch is in progress and if a branch was guessed. An operational code compression means forms each instruction into a new operation code of lesser bits and embeds a guess bit into the new operational code. Control means decode the compressed operational code as an input to an instruction execution unit whereby conditional branch occurs based on the guess bit provided a branch instruction is not in progress in the system.

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Apex, NC, United States of America

Bryan Keith Bullis