Advanced Micro Devices Corporation

Spansion Llc.

Other

Cypress Semiconductor Corporation

Bryan K Choo

Bhanwar Singh

Sanjay K Yedur

Ramkumar Subramanian

Bharath Rangarajan

Khoi A Phan

Michael K Templeton

Fei Wang

Steven C Avanzino

Sameer S Haddad

Jeffrey Allan Shields

Suzette Keefe Pangrle

Manuj Rathor

James J Xie

Carmen L Morales

Michael Vanbuskirk

Christie Marrian

Kevin Song

Matthew S Buynoski

Calvin T Gabriel

Joong Jeon

Wen Yu

Ercan Adem

Robert J Chiu

David H Matsumoto

Subash Gupta

Jeffery A Shields

Winny Stockwell

James Xie

A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Damascene metal-insulator-metal (MIM) device with improved scaleability

The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Damascene metal-insulator-metal (MIM) device

In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

Thin film germanium diode with low reverse breakdown

The present invention relates to visually monitoring an interior portion of a processing chamber in a semiconductor processing system. An image collector collects images of the interior of the chamber and provides an image signal indicative of a visual representation of the interior of the chamber. A viewing station receives the image signal and displays a visual representation of the interior of the chamber.

System and method for visually monitoring a semiconductor processing system

A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. One or more structures formed on a wafer matriculating through the process facilitate concurrent measurement of critical dimensions and overlay via scatterometry or a scanning electron microscope (SEM). The concurrent measurements mitigate fabrication inefficiencies, thereby reducing time and real estate required for the fabrication process. The measurements can be utilized to generate feedback and/or feed-forward data to selectively control one or more fabrication components and/or operating parameters associated therewith to achieve desired critical dimensions and to mitigate overlay error.

Concurrent measurement of critical dimension and overlay in semiconductor manufacturing

A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.

Using scatterometry to obtain measurements of in circuit structures

The present invention provides a system and method for detecting and repairing defects in semiconductor devices. According to the invention, defects are located using a scanning probe microscope, such as an atomic force microscope or a scanning tunneling microscope, and repaired at locations determined by the scanning probe microscope. The microscope itself, and in particular the detection tip, may be employed to remove the defects. For example, the tip may be used to machine away the defect, to apply an electric field to oxidize the defect, and/or to heat the defect causing it to burn or vaporize. By combining precise defect location capabilities of a scanning probe microscope with defect removal, the invention permits very precise correction of defects such as excess material and foreign particles on semiconductor substrates.

Use of scanning probe microscope for defect detection and repair

A system for evaluating optical proximity corrected (OPC) designs is provided. The system includes an analysis system for performing measurements relating to a segment of a feature. The analysis system is configured to determine a first image for the segment of the feature based upon the measurements. The analysis system determines a second image to facilitate analysis of the first image and evaluates OPC designs based upon comparisons of the first and second image.

Optimization of OPC design factors utilizing an advanced algorithm on a low voltage CD-SEM system

A system and method is provided for applying a developer to a photoresist material wafer disposed on a semiconductor substrate. The developer system and method employ a developer plate having a plurality of a apertures for dispensing developer. Preferably, the developer plate has a bottom surface with a shape that is similar to the wafer. The developer plate is disposed above the wafer and substantially and/or completely surrounds the top surface of the wafer during application of the developer. A small gap is formed between the wafer and the bottom surface of the developer plate. The wafer and the developer plate form a parallel plate pair, such that the gap can be made small enough so that the developer fluid quickly fills the gap. The developer plate is disposed in very close proximity with respect to the wafer, such that the developer is squeezed between the two plates thereby spreading evenly the developer over the wafer.

Parallel plate development

The present invention provides SEM calibration standards, and associated SEM systems and SEM calibration methods, that are self-cleaning with respect to electron beam deposited carbon. The calibration standards have coatings containing a transition metal oxide. The coatings facilitate oxidation of deposited carbon, whereby carbon buildup can be stopped or reversed. By providing a mechanism to mitigate carbon buildup, calibration standards provided by the present invention achieve high accuracy, high durability, and low cost.

Self-cleaning technique for contamination on calibration sample in SEM

The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A light emitting diode is located in the chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.

System and method for illuminating a semiconductor processing system

The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.

Carbon nanotubes as linewidth standards for SEM & AFM

The present invention relates to illuminating an interior portion of a processing chamber in a semiconductor processing system. A fiber optic light source is operatively associated with the processing chamber to illuminate the interior of the chamber to facilitate viewing the interior of the chamber.

The present invention provides a system and method that facilitates measuring and imaging topographical features of a substrate, including lines and trenches having reentrant profiles. One aspect of the invention provides an electron microscope that simultaneously scans a substrate with two or more electron beams that are directed against the substrate with substantially differing angles of incidence. Secondary electrons resulting from the interaction of the substrate with the beams are detected by one or more secondary electron detectors. Each secondary electron detector may simultaneously receive secondary electrons resulting from the interaction of the substrate with two or more electron beams. In another of its aspects, the invention provides methods of analysis that permit the interpretation of such data to analyze critical dimensions and form images of the substrate. Critical dimensions that may be determined include feature heights and reentrant profile shapes. The topographical information provided is more complete than that of conventional SEM imaging and is obtained more rapidly than would be possible using multiple scans of a single electron beam.

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Mountian View, CA, United States of America

Bryan K Choo