Intel Corporation

Bryan K Casper

James E Jaussi

Stephen R Mooney

Aaron K Martin

Ganesh Balamurugan

Mozhgan Mansuri

Frank Patrick O'Mahony

Joseph T Kennedy

Matthew B Haycock

Tawfiq Musah

Howard L Heck

Chintan S Thakkar

Shekhar Yeshwant Borkar

James A McCall

Christopher P Mozak

David Stewart Dunning

Debabani Choudhury

Tzu-Chien Hsueh

Shilpa Talwar

Kameran Azadet

Hosein Nikopour

Ofir Degani

Wook Bong Lee

Ashoke Ravi

Michael Genossar

Claudio Da Silva

Stefano Pellerano

Frank T Hady

Rotem Banin

Albert Molina

Sidharth Dalmia

Georgios Yorgos Palaskas

Igal Kushnir

Duncan Kitchin

Oner Orhan

Saku Lahti

Emanuel Cohen

Mikko S Komulainen

Gadi Shor

Jayprakash Thakur

Eren Sasoglu

Arnaud Lucres Amadjikpe

Menashe Soffer

Kunal Datta

Moshe Teplitsky

Ana M Yepes

Omer Asaf

Run Levinger

Eshel Gordon

Josef Hagn

Erkan Alpman

Nebil Tanzi

Ron Pongratz

Baljit Singh

Peter Sagazio

Eyal Goldberger

Amit Freiman

Shuhei Yamada

Eran Gerson

Yossi Tsfati

Shmuel Ravid

Kaushik Dasgupta

Nir Weisman

Noam Kogan

Resti Montoya Moreno

Meir Gordon

Marian K Verhelst

Anandaroop Chakrabarti

Miroslav Baryakh

Navneet Dour

Gokce Keskin

Roger K Cheng

Sami Hyvonen

Ajay Balankutty

Dave Dunning

Sujit Sharan

Christopher J Hughes

Debendra Mallik

Srinivas V Pietambaram

Tanay Karnik

Kristof Darmawikarta

Rahul N Manepalli

Zhichao Zhang

Yen-Kuang Chen

Eyal Fayneh

Gang Duan

Zeshan A Chishti

Changkyu Kim

Xiaoqian Li

Gregory W Chance

Bai Nie

Brandon R Davis

Jason M Gamba

Sameer Paital

Arnab Sarkar

Timothy M Wilson

Kenneth Brown

Anthony-Trung D Nguyen

Divya Pratap

Suresh V Pothukuchi

Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

High bandwidth optical interconnection architectures

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

Wireless communication technology, apparatuses, and methods

An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL)

Embodiments disclosed herein include waveguides. In an embodiment, a waveguide comprises a conductive shell and a first ridge within the conductive shell. In an embodiment, the first ridge extends away from the conductive shell. In an embodiment, the waveguide further comprises a first core over the first ridge, where the first core comprises a first dielectric material with a first permittivity. In an embodiment, the waveguide may further comprise a second core embedded in the first core, where the second core comprises a second dielectric material with a second permittivity that is greater than the first permittivity.

Waveguides including at least one ridge associated with at least one dielectric core and the waveguides are surrounded by a conductive shell

A digital transmitter architecture is disclosed to transmit (TX) multi-gigabit per second data signals on single carriers (SC) or orthogonal frequency division multiplexing (OFDM) carriers at millimeter wave frequencies in either one of a high-resolution modulation mode or a spectral shaping mode. The architecture includes a number of digital power amplifier (DPA) and modulation reconfigurable circuit segments to process individual bits of a data bit stream in parallel according to a specific circuit configuration corresponding to the selected TX mode using a multiplexer to switch between configurations.

Ultra-high data rate digital mm-wave transmitter with energy efficient spectral filtering

Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

Reconfigurable transmitter

Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Systems, methods, and apparatuses for stacked memory

Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted ('noninverted signal') and a number and/or ratio of ones and zeros in an inverted version of the signal ('inverted signal'). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and zeros in signal lines

Described is an apparatus which comprises: a Variable Gain Amplifier (VGA); a set of samplers to sample data output from the VGA according to a clock signal; and a Clock Data Recovery (CDR) circuit to adjust phase of the clock signal such that magnitude of a first post-cursor signal associated with the sampled data is substantially half of a magnitude of a primary cursor tap associated with the sampled data.

Low power high speed receiver with reduced decision feedback equalizer samplers

Growing community of inventors

Hillsboro, OR, United States of America

Bryan K Casper