Texas Instruments Corporation

Intermedics Inc.

Bryan Joseph Thome

Gary L Swoboda

Manisha Agarwala

Dipan Kumar Mandal

Lewis Nardini

Gary A Cooper

John M Johnsen

William B Rottenberg

James K Fox

Kanika Ghai Bansal

Maria B H Gill

An electronic tracing process includes packing both stall () and reason () data into a single high priority timing information stream. An integrated circuit includes an electronic processor (), and a tracing circuit () operable to pack both stall and events data into a single timing information stream. Other circuits, processes and systems are also disclosed.

Embedding stall and event trace profiling data in the timing stream

Introducing timing synchronization indicating stall reason in next synchronization window

Prioritizing stall/reason data into priority information stream over PC/data trace

A method and/or a system of a processor-agnostic encoded debug architecture in a pipelined environment is disclosed. In one embodiment, a method of a processor includes processing an event specified by a data processing system coupled to the processor to determine a boundary of the event, generating a matrix having combinations of the event and other events occurring simultaneously in the processor, capturing an output data of observed ones of the event and other events, and applying the matrix to generate an encoded debug data of the output data. The method may also include determining which of the combinations are valid based on an architecture of the processor. The event may be a trace-worthy event whose output value cannot be reliably predicted in an executable file in the data processing system and/or a sync event that is specified by a user of the data processing system.

Serialization module separating pipelined trace-worthy event and sync packet data

During a trace the timing stream has the active and stall information, PC stream has all the discontinuity information, and the data stream has all the data log information. The various streams are synchronized using markers called sync points. The sync points provide a unique identifier field and a context to the data that will follow it. After data corruption a sync point is inserted into the data stream. The ID of this sync point may repeat a previous sync point ID.

Method for generating timing data packet

Data system simulated event and matrix debug of pipelined processor

The present disclosure describes systems and methods for multiplexing multiple data sources Some illustrative embodiments include a method for combining multiple data sources, including building one or more single-source data words by iteratively selecting a data source, writing data from the data source to each data section within a single-source data word if enough data is available to fill the single-source data word, copying a data bit of the single-source data word to a data bit within a start word, and clearing the data bit of the single-source data word; and including transmitting the one or more single-source data words after transmitting both a start word and one or more multi-source data words within the same data frame The data written into the one or more single-source data words and the data most recently written into the one or more multi-source data words originate from the same data source.

Systems and methods for multiplexing and demultiplexing multiple data sources

A multiprogrammer system, for monitoring and optimizing implant performance, includes at least two programmers and an implant. Each programmer may perform inquiry and programming operations on the implant. In an inquiry operation, the programmer retrieves some or all of the configuration parameters from the implant. In a programming operation, the programmer provides one or more modified parameters to the implant. As part of the programming operation, the programmer is configured to verify that it is aware of the implant's current parameters before sending modified parameters. The current programmer verifies that the implant's parameters have not been altered since the current programmer's last interaction with the implant. If the parameters have been altered, the current programmer aborts the programming operation and provides notification. The verification may be performed by the implant, i.e., it may verify that the programmer is aware of the current device parameters before the implant accepts modified parameters.

Implantable device and programmer system which permits multiple programmers

In a test and debug system, a plurality of trace streams, including a timing trace stream, are transmitted from the target processing unit to the host processing unit for analysis. The timing trace stream, the trace stream that indicates activity or non-activity of the program counter each clock cycle, can occupy a large percentage of the bandwidth of the transmitted data. The transmitted data is organized into groups of packets, each packet having a control signal portion and a payload portion. Each information packet has a logic signal stored at each location indicating an activity or a non-activity of the program counter. By identifying portion of the timing trace stream wherein the activity or non-activity does not change for one or more groups of timing packets, the information in a plurality of packets can be represented by a header and an information packet that describes a number of packets in which the activity or non-activity of the program counter does not change.

Apparatus and method for compression of the timing trace stream

When an INTERRUPT SERVICE ROUTINE (SECONDARY) CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the INTERRUPT SERVICE ROUTINE CODE FLUSH signal. The interrupt service routine code flush sync marker identifies the absolute program counter address at the time of the generation of the INTERRUPT SERVICE ROUTINE CODE FLUSH signal and relates the INTERRUPT SERVICE ROUTINE CODE FLUSH signal sync marker to a timing trace stream. The INTERRUPT SERVICE ROUTINE CODE FLUSH signal is generated at the transition between the interrupt service routine (secondary) code instructions being removed from the pipeline flattener and the program (primary) code instructions being removed from the pipeline flattener.

Apparatus and method for trace stream identification of a pipeline flattener secondary code flush following a return to primary code execution

When a plurality of simultaneous, preselected target processor events are detected, a multiple-event sync marker is generated that identifies the preselected events and relates the occurrence of these events to timing trace stream. The sync marker for the plurality of preselected events differs from a single event sync marker by including at least one additional packet. The additional packet includes logic signals stored at locations related to each identified event.

Apparatus and method for trace stream identification of multiple target processor events

A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.

Tracing program counter addresses using native program counter format and instruction count format

When a DEBUG HALT signal is generated in a target processor during a test procedure, a debug halt sync marker is generated in a program counter trace stream. The debug halt sync marker includes a plurality of packets, the packets identifying that the sync marker is the result of a DEBUG HALT signal. The packets also identify the program counter address at the time of the generation of the DEBUG HALT signal and relate the debug halt sync marker to a timing trace stream.

Apparatus and method for trace stream identification of a processor debug halt signal

When a RESET signal is generated in a target processor during a test procedure, a reset sync marker is generated in a program counter trace stream. The reset sync marker includes a plurality of packets, the packets identifying that the reset sync marker is the result of a RESET signal. The packets identify the program counter address at the time of the generation of the RESET signal and relate the reset sync marker to a timing trace stream. When the RESET signal is removed, a second (reset-off) sync marker is generated identifying the removal of the RESET signal, identifying the program counter address, and relating the second sync marker to the timing trance stream.

Apparatus and method for trace stream identification of a processor reset

When a NEW SECONDARY CODE EXECUTION START POINT signal is generated in a target processor during a test procedure after the return from an interrupt service routine (i.e., an original secondary code sequence), a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the NEW SECONDARY CODE EXECUTION START POINT signal. The new secondary program code start point sync marker identifies the absolute program counter address at the time of the generation of the NEW SECONDARY CODE EXECUTION START POINT signal and relates the NEW SECONDARY CODE EXECUTION START POINT signal sync marker to a timing trace stream.

Growing community of inventors

Houston, TX, United States of America

Bryan Joseph Thome