Rambus Inc.

Syphermedia International, Inc.

Cryptography Research, Inc.

Other

Verimatrix, Inc.

Bill.com, Inc.

Inside Secure S.a.

Promtek Programmable Memory Technology, Inc.

Bryan Jason Wang

James Peter Baukus

Ronald Paul Cocchi

Lap Wai Chow

Winthrop Wu

Samatha Gummalla

Changlin Zhang

Akshay Ukey

Sangam Singh

Scott C Best

Marufa Kaniz

Guilherme Ozari De Almeida

Paul Ouyang

Joel Patrick Wittenauer

Qinglai Xiao

Ashish Raj

Thomas J Thatcher

A request to perform a memory operation addressed to a first address corresponding to a first logical unit of logical units of a memory is received. Address mask data that corresponds to the logical units is identified. Multiple transformed addresses are determined using the first address and the address mask data. The transformed addresses can include a target address corresponding to the first logical unit and additional addresses corresponding to other logical units. The memory operation is performed at the target address corresponding to the first logical unit and dummy memory operations are performed at the additional addresses corresponding to the additional logical units.

Obfuscation of data in a memory

Technologies for detecting and classifying errors detected in pipelined hardware are described. One device includes a hardware pipeline with a set of pipeline stages. Error detection logic can detect an error in the hardware pipeline, and control logic can classify the error in one of the multiple categories based on a type of the error, a position of the first data in a data stream that triggered the error, and a position of a pipeline stage in which the error is detected. The control logic can perform an error-response action based on the error classification of the error.

Pipelined hardware error classification and handling

A DMA system includes two or more DMA engines that facilitate transfers of data through a shared memory. The DMA engines may operate independently of each other and with different throughputs. A data flow control module controls data flow through the shared memory by tracking status information of data blocks in the shared memory. The data flow control module updates the status information in response to read and write operations to indicate whether each block includes valid data that has not yet been read or if the block has been read and is available for writing. The data flow control module shares the status information with the DMA engines via a side-channel interface to enable the DMA engines to determine which block to write to or read from.

Data flow control module for autonomous flow control of multiple DMA engines

Multiple (e.g., two) hosts access a single memory channel (and/or device) via a memory controller. The single memory channel/device can support at most one access at a time. To reduce contention between the multiple hosts, the memory controller comprises multiple (e.g., two), independent, host ports. Each host port is associated with a write buffer(s) in the memory controller that stores write data at least until the memory controller writes the data to the memory channel. Data stored in a write buffer may be used to respond to memory access commands (e.g., reads or writes) on the ports without accessing the memory channel. In this manner, the hosts do not directly contend with each other for the single memory channel or the memory controller.

Multiple host memory controller

A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine. The host device generates a command table for batch processing of a set of address tables that each describe a set of data blocks of a file to be encrypted or decrypted. The DMA engine facilitates a DMA transfer of the command table from the host memory to an RoT memory of the RoT device. The RoT device then performs batch processing of the address tables referenced in the command table. For each address table, the DMA engine copies a set of data blocks from the host memory to the RoT memory, a cryptographic engine encrypts or decrypts the data blocks, and the DMA engine copies the transformed data blocks back to the host memory.

Batch transfer of commands and data in a secure computer system

Methods, systems, and computer storage media are provided for data extraction. A target document representation may be generated based on modified text of a target electronic document. A measure of similarity may be determined between the target document representation and a reference document representation, which may be based on modified text of a reference electronic document. Based on the measure of similarity, the reference document representation may be selected. An extraction model associated with the selected reference document representation can then be used to extract data from the target document.

Electronic document data extraction

A camouflaged application specific integrated circuit is disclosed. The camouflaged ASIC includes at least one camouflaged FinFET, which includes a substrate of a first conductivity type, a fin, disposed on the substrate, the fin including a source region of a second conductivity type, a drain region of the second conductivity type, and a channel region of the first conductivity type. The camouflaged application specific integrated circuit also includes a gate disposed over and substantially perpendicular to the channel region, forming one or more transistor junctions with the fin. In one embodiment, the substrate includes a punch through stop (PTS) region of the second conductivity type disposed between the fin and the substrate, the PTS region electrically shorting the source region of the fin to the drain region of the fin.

Always-on FinFET with camouflaged punch stop implants for protecting integrated circuits from reverse engineering

A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.

Electrically isolated gate contact in FINFET technology for camouflaging integrated circuits from reverse engineering

An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.

Physically unclonable camouflage structure and methods for fabricating same

The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.

Secure logic locking and configuration with camouflaged programmable micro netlists

A camouflaged FinFET is disclosed. The camouflaged FinFET comprises a fin and a gate, disposed over and perpendicular to the fin. The fin includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, the channel region disposed between the source region and the drain region, and a camouflaged fin region of the second conductivity type, the camouflaged Fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.

Camouflaged FinFET and method for producing same

A method and an apparatus for camouflaging an application specific integrated circuit are disclosed. The ASIC comprises a circuit comprising a plurality of interconnected functional logic cells performing a logical function. In one embodiment, the method comprises accepting a coded description of the circuit, wherein the coded description describes the circuit in terms of components comprising a sequential logic component and a virtual camouflage component, generating a logical description of the circuit, the logical description of the circuit comprising a logical description of the virtual camouflage component, and replacing, in the logical description of the circuit, the logical description of the virtual camouflage component with a logical description of a functionally equivalent technology-dependent camouflaged component.

Growing community of inventors

South Lake Tahoe, CA, United States of America

Bryan Jason Wang