3com Corporation

Hewlett-packard Development Company, L.p.

Bryan J Donoghue

David J Law

Eugene O'Neill

Kam Choi

Edele O'Malley

Paul J Moran

Jerome Nolan

Edward Turner

Quang T Tran

Maurice A Goodfellow

Alan R Poulter

Richard N Bayfield

Tin Lam

Lee C Harrison

Mark A Bobbitt

Richard A Gahan

Maunte A Goodfellow

Victoria A Griffiths

Benjamin J O Kerr

In one embodiment, a method is described for detecting an operational failure between the network unit and an adjacent network unit in the stack; controlling the switching engine to redirect packets which would otherwise be sent from a particular port to the adjacent network unit to be forwarded from another port to be sent to a different network unit in the stack; and entering the switching engine into a bypass mode in response to control data indicating an operational failure between at least two other network units in the stack to cause packets to be forwarded without being re-directed by the switching engine.

Cascade system for network units

A network stack includes a plurality of network units each of which includes a multiplicity of ports for receiving and forwarding addressed data packets, at least two cascade ports and a switching engine for forwarding received packets to at least one port in accordance with address data in the packets and a cascade connection including, for each of two opposite directions around the stack, at least one unidirectional path for data packets composed of links each between a respective cascade port on a network unit and a corresponding cascade port on the next network unit.

A system of switch modules contains input demultiplexers connected to ports on each of the modules and output multiplexers connected to each of the modules. Each module has output and input interfaces for mesh links and at least one output interface is looped back to an input interface on the same module. The arrangement reduces module-to-module traffic and corresponding increases the transmit bandwidth of a module.

High-speed switch architecture

Network units such as switches for use in a cascaded stack are organised to provide a cascade connection in the form of a dual unidirectional connection so that, in its ordinary configuration, there is at least one and preferably more than one unidirectional ring for each direction around the cascade, each ring including a respective port on each unit. For each ring, each port on a unit is connected by a respective link to a corresponding port on the preceding unit and the following unit. The units provide a self-healing operation in the event of various kinds of operational failure. The self-healing operation includes loop-back of packets in units adjacent the failure and bypass of a packet switching process for other units. The units include control logic for passing control frames containing status information relating to the units and links between them and for co-operation with a CPU to control a switching engine to perform the self-healing operation in accordance with that status information. The units forward on the cascade packets with headers that identify a destination port and the unit on which that port is located and also indicate which units have and have not been traversed by a packet.

An interface between a wireless node and a network node includes an encapsulator for temporarily converting data frames into Ethernet frames for the link between the two nodes and de-encapsulating the Ethernet frames before the data is processed at the network node.

Interface system for wireless node and network node

Cascade control logic for use in a switch or other network unit that can be used in a cascaded stack can maintain normally a point-to-point half-duplex connection for control data with each of the next preceding and next succeeding units in the cascade. Each cascade logic device is organised so that for one direction, conveniently called the up direction, a device is a master and in the other direction the device is a slave in respect of the control path. A control device will generate master control frames in the up direction and deliver slave control frames in the down direction. The control device is organised so that in the absence of reception of valid control frames on a control link control data which would otherwise be sent out on that link is looped back within the control device. In this manner the control device can maintain under normal circumstances two virtual control channels which can 'self-heal' notwithstanding the failure or powering-down of a unit in the cascade. Status information represented by the control frames can be used to control a switching engine to provide self healing of the data path in the cascade.

Cascade control system for network units

A network device which includes means for receiving data packets over a link, a memory for the packets, means for providing an indication that the occupancy of the memory is less than a first watermark, and means responsive to the indication for providing a sequence of pause frames comprising an alternating sequence of XOFF frames defining a very long cessation of the sending of packets and XON frames defining substantially zero cessation of the sending of packets. The means for providing the pause frames is responsive to the increase of the occupancy of the memory above a selected watermark to cease the provision of the sequence of pause frames.

Flow control system for network devices

A data processor and storage system which comprises a data processor, a cache memory and a main memory is arranged so that the addressing of the main memory produces a multiplicity of spaced aliases, the multiplicity being greater than the set-associativity of the cache memory. The cache memory may be a multiple way set associative cache memory with the system including a round robin allocator for controlling the storing of successive data items in the different ways of the set associative cache. The cache may also be a direct mapped cache having single way set-associativity so that the round robin allocator is not required. The system may also include a direct memory access (DMA) device for copying data items into the memory. The memory may be a buffer memory which is divided into a plurality of packet buffers.

Date processor and storage system including a set associative cache with memory aliasing

Printed circuit board

A printed circuit board which has in a first edge a first notch and a second notch a first predetermined distance apart and along said first edge between said first and second notches a plurality of terminal pads in a broadside array, the first edge including a third notch spaced from the second notch and disposed a second predetermined distance, greater than the first predetermined distance, from said first notch, the board having along and adjacent the first edge between the second and third notches a second plurality of terminal pads arranged in a respective broadside array.

Growing community of inventors

St. Albans, United Kingdom

Bryan J Donoghue