Credence Systems Corporation

Credence Systems Coporation

Bryan J Dinteman

Paul Dana Wohlfarth

Daniel J Bedell

Roman A Slizynski

Charles C Warner

Robert R Hale

David Dean Reynolds

A timing signal generator including a direct digital frequency synthesizer (DDFS), a divide-by-N counter, and a pattern generator, produces a TIMING signal conveying a timed sequence of pulses. The pattern generator produces a sequence of data pairs (FREQ,N), with each pair being produced in response to each pulse of the TIMING signal and indicating a time interval that is to occur between that TIMING signal pulse and a next TIMING signal pulse. The DDFS produces an output sine wave signal (SINE) having a frequency controlled by the current FREQ data output of the pattern generator. The divide-by-N counter produces the timing signal pulses. It counts cycles of the SINE signal occurring since it last produce a TIMING signal pulse and generates a next TIMING signal when it has counted the number of SINE signal pulses indicated by the current N data output of the pattern generator.

Timing signal generator employing direct digital frequency synthesis

A low-profile, short signal path relay assembly implementing several relays for use in an integrated circuit tester, a digitizer or other equipment requiring multiple relays, includes a chassis and a signal board mounted within the chassis. Each relay includes a control rod slideably mounted within the chassis above the signal board, a resilient contact arm mounted on the signal board below the control arm, and a coil assembly mounted adjacent to a magnetic end of the control rod. A spring is positioned between the control rod and the chassis so that it normally forces the control rod to slide in a direction away from the coil assembly. However when a current is applied to the coil assembly it produces a magnetic flux attracting the magnetic end of the control rod toward the coil assembly. As it moves toward the coil assembly, the control rod presses down on the relay's contact arm causing it to contact a pad on the surface of the signal board, thereby creating a signal path through the relay arm between two points on the signal board. When the coil current is turned off, the spring pushes the control rod away from the coil assembly so that it no longer presses on the relay arm. The relay arm thereupon breaks its contact with the pad.

High frequency relay assembly for automatic test equipment

An integrated circuit (IC) tester includes a set of dual-purpose digital/analog channels. Each tester channel includes a driver capable of supplying either a digital or analog test signal input to an IC terminal and a receiver for digitizing and processing either an analog or digital IC output signal appearing at the DUT terminal to produce results data representing the behavior of that IC output signal during a test. A test is organized into a succession of test cycles, and before each test cycle a pattern generator within each channel produces data for controlling the behavior of the driver and receiver during the test cycle. The control data controls whether the driver is to produce an analog or a digital test signal, controls a magnitude or logic level to which the test signal is to be driven during the test cycle, and controls a time during the test cycle of any test signal state or magnitude changes. The control data also indicates how and when the receiver digitizes and processes an IC output signal during the test cycle.

Integrated circuit testing device with dual purpose analog and digital channels

An integrated circuit (IC) tester includes a set of digital and analog channels, each of which may be programmed to carry out a sequence of test activities at pins of an IC under test. The channels are interconnected by a trigger bus, and each channel may be programmed to respond to a detected event during a test by transmitting a particular trigger code to every other channel via the trigger bus. Each channel may be also programmed to respond to a particular trigger code arriving on the trigger bus by branching its sequence of test activities. Thus any channel detecting an event during a test can signal all other channels to immediately terminate a current sequence of test activities and branch to another set of test activities. Such a conditional branch capability enables the tester to automatically perform an 'if/then' diagnostic test on an IC in which a test result detected at any point during the test determines the future course of the test.

Integrated circuit tester with real time branching

A triggered clock signal generator produces a periodic output clock signal (CLOCK3) in response to an input TRIGGER signal, wherein a delay between the TRIGGER signal and the first pulse of the CLOCK3 signal is accurately adjustable. The apparatus includes a period generator and a phase adjuster. The period generator, using a periodic input signal (CLOCK1) as a timing reference, responds to the TRIGGER signal by producing a periodic output clock signal (CLOCK2) in adjustably delayed response to a next pulse of the CLOCK1 signal. The phase adjuster phase shifts the CLOCK2 signal to produce the CLOCK3 signal. The phase adjuster compares the phase of the CLOCK1 signal to the phase of the TRIGGER signal to determine an appropriate amount by which to phase shift the CLOCK2 signal so that the time delay between the TRIGGER signal and the first pulse of the CLOCK3 signal is independent of the phase relation between the TRIGGER and CLOCK1 signals.

Triggered clock signal generator

A drive circuit for an integrated circuit tester operates in either a drive mode of a termination mode. In the drive mode, the drive circuit supplies a differential test signal to an integrated circuit device under test (DUT) via a pair of transmission lines. In its termination mode, the drive circuit terminates the transmission lines with their characteristic impedances and provides an adjustable load to a DUT output signal appearing on the transmission lines.

Inhibitable continuously-terminated differential drive circuit for an

A general purpose integrated circuit (IC) tester includes a set of channels, one for each input or output pin of an IC device under test (DUT). Each channel is programmed by a host computer to either supply a test signal to a DUT I/O pin or sample a DUT output signal appearing at the I/O pin and produce sample data representing its magnitude or logic state. The tester also includes an amorphous logic circuit (ALC) having a set of input and output terminals and a programmable logic circuit interconnecting the input and output terminals. Some of the ALC input and output terminals receive the sample data produced by each channel and other ALC terminals send control signals directly to each channel. Other ALC terminals transmit data to the host computer. When it programs the channels to perform a test, the host computer also programs the ALC to control various operations of the channels during the test, to perform a real-time analysis of the test data produced by the channels, and to communicate results of the analysis to the host.

Integrated circuit tester having amorphous logic for real-time data

A digitizer can be programmed to digitize an ANALOG signal with a complex frequency pattern determined in response to set of trigger signals. The digitizer includes an addressable packet memory storing a set of data packets and produces one of its stored data packets as output when addressed. The output data packet includes both PERIOD and MODE data fields. The digitizer also incudes an analog-to-digital converter for digitizing the ANALOG signal at the frequency controlled by the PERIOD data output of the packet memory. The MODE data output of the packet memory tells a trigger logic circuit how to choose a next packet memory address and selects one of the trigger signals to tell the trigger logic circuit when to change the packet memory address so as to alter the digitizing frequency.

Programmable digitizer with adjustable sampling rate and triggering modes

A differential driver includes an input stage and an output stage. The input stage receives a differential INPUT signal to produce a differential DRIVE signal of state determined by the INPUT signal. The output stage receives the DRIVE signal and produces a differential OUTPUT signal of state determined by the DRIVE signal. The OUTPUT signal voltage can be adjusted within any of multiple ranges. The output stage adjusts its output load resistance for each OUTPUT signal voltage range in order to maximize operating speed while limiting power consumption in each range. The input stage automatically reduces the voltage of the DRIVE signal input to the output stage for low OUTPUT signal voltages to reduce noise in the OUTPUT signal.

Differential driver having multiple output voltage ranges

A drive circuit for an integrated circuit tester produces an output test signal in response to an input sequence of vector data values, wherein each vector data value references a test signal state and a time at which the test signal is to change to the referenced state. The drive circuit includes decoding and timing circuits for producing an indicating signal (D) of the state referenced by each incoming vector data value and a timing signal (TD) having a pulse occurring at the time referenced by the incoming vector data value. An event phase modulator within the drive circuit stores a control bit indicating the state of the indicating signal in response to each pulse of the timing signal. The event phase modulator waits for a variable amount of time after storing each control bit and then forwards the control bit to the input of a driver producing the test signal. The driver sets the test signal state in accordance with the state of the control bit. The delay between the time the event phase modulator stores a control bit and forwards it to the driver is a function of time determined by input programming data. Thus the event phase modulator phase modulates the test signal in a manner determined by its input programming data.

Event phase modulator for integrated circuit tester

Inhibitable, continuously-terminated differential drive circuit for an

Apparatus for testing an integrated circuit device (DUT) having an input port and an output port comprises multiple state devices each having multiple states that occur in a predetermined sequence and each having an output port at which it provides an event signal representative of its current state. At least a first of the state devices is an emitting device that emits an event marker signal at a predetermined time in advance of entering a predefined state, at least a second of the state devices is a receiving device that responds to receipt of an event marker signal in a predetermined manner after lapse of a predetermined time, at least one of the state devices has its output port connected to the input port of the DUT, and at least one of the state devices is a measurement device connected to the output port of the DUT. An interconnection matrix is connected to each state device and allows each state device to communicate an event marker signal to each other state device.

Growing community of inventors

Canby, OR, United States of America

Bryan J Dinteman