Agilent Technologies, Inc.

Bryan Haskin

Gayvin E Stong

Jason Todd Gentry

David D Balhiser

Ronald G Harber

Paul J Marcoux

A receiver method and apparatus is presented. Signals are received from a high-voltage environment to a low-voltage environment using low-voltage devices, such as low-voltage FETs. A reference stage (i.e., first stage) provides the reference point for an input signal that is received into a second stage. The reference stage works in conjunction with the second stage to control the output of the second stage. The reference stage and the second stage communicate through floating voltage signals. The output of the second stage is an inverted signal that floats. A third stage receives the inverted signals and corrects the signal to a baseline (i.e., adds gain to the signal). The signal is then clipped by a clipping stage (i.e., fourth stage). The clipping stage clips the high-voltage signal so that it will operate with the devices in the low-voltage environment. A fifth stage is then biased with a low voltage and the clipped signal is shifted downwards. Lastly, an inverter (i.e., sixth stage) receives the signal that has been shifted downward and outputs the signal to an output node.

Stacked FET receiver method and apparatus

A method of comparing two rectangles of a circuit design structure for overlap is provided. The two rectangles being compared are modified conceptually in such a way as to reduce the amount of computation necessary to determine if the two rectangles overlap. In one embodiment, a first rectangle is reduced in both x- and y-directions to a single point residing in the center of that rectangle, while the size of the second rectangle is expanded in both x- and y-directions by the same amount, resulting in an enlarged rectangle. A determination of whether the single point resides within the enlarged rectangle thus indicates if the two original rectangles overlap. Similarly, in another embodiment, a first rectangle is reduced in the x-direction only, resulting in a y-directed line segment, while a second rectangle is reduced in the y-direction, resulting in an x-directed line segment. The y-directed line segment is extended by the amount that the second rectangle was reduced in the y-direction, and the x-directed line segment is extended by the amount that the first rectangle was reduced in the x-direction. A determination of whether the x-directed line segment and the y-directed line segment intersect indicates if the first and second rectangles overlap.

Method for determining whether two rectangles of an electronic circuit structure overlap

A method and system of identifying one or more nets in a digital IC design that are at risk of electromigration comprises selecting a manufacturing process for the digital IC design and obtaining a clock period and process voltage. A voltage waveform transition time and effective capacitance is calculated for one or more of the nets. A maximum allowable effective capacitance for each one of the nets is calculated based upon a peak current analysis or an RMS current analysis. The effective capacitance for each net is compared against the maximum allowable capacitance to identify those nets that are at risk of failure due to the effects of electromigration.

Process and system for identifying wires at risk of electromigration

A method and apparatus for interfacing two voltage domains is presented. In one embodiment of the present invention, a method and apparatus for interfacing a high voltage domain with a low voltage domain is presented. In one embodiment of the present invention, high output signals and low output signals are generated with a level-shifter. The level-shifter is used to interface the two domains. The low output signals are generated using a low-voltage driver and a first clipping stage. The high output signals are generated using a high-voltage driver and a second clipping stage. Duty-cycle distortion is lowered or eliminated by using an accelerator to accelerate the transition between the high output signals and the low output signals. Bias signals are input into the first and second stage. The bias signals work in a coordinated manner, to constrain the minimum and maximum outputs of various components in the level-shifter.

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Fort Collins, CO, United States of America

Bryan Haskin