Altera Corporation

Other

Altera Corporaton

Bryan H Hoyer

Michael Fairman

Tim Allen

Jeffrey Orion Pritchard

Andy Louie Lee

Kerry S Veenstra

Keith Duwel

Chris Lane

Mario E Guzman

John Yin

Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.

Methods and apparatus for implementing parameterizable processors and peripherals

For synchronizing a master device and a slave device connected by a data transfer link, the master device measures a phase offset in a signal received from the slave device with respect to the master's clock signal. The master determines a control symbol based on the phase offset. The master encodes the control symbol in a transmit signal for the slave. The slave decodes the control symbol from the signal received from the master. The slave uses the control symbol to adjust the phase shift to compensate for the phase offset of a signal to be transmitted to the master device. When the phase compensated signal is received at the master, its phase offset is smaller than the original phase offset. This procedure can be performed iteratively until the phase offset is within a desired tolerance.

Clock data recovery and synchronization in interconnected devices

A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

Reconfigurable programmable logic system with configuration recovery mode

Internal registers of a PLD are exposed for debugging using a JTAG port and a scan chain. The user of a PLD identifies registers at the source code level. These registers are automatically inserted in a scan chain. An EDA software tool provides a means of choosing a register from the electronic design. The EDA tool connects the selected register to the JTAG scan chain and passes information to the software about the location in the scan chain. The EDA tool provides for scanning of the chain under automatic or manual control. The selected nodes are extracted from the chain and displayed in a user-specified format. Registers in encrypted blocks are exposed. The vendor of the block decides which registers are of importance. Once selected, the vendor creates a &ldquo;debugging&rdquo; file which is delivered to the customer along with the encrypted block. The debugging file contains the names of the registers, their data type, and their symbolic values.

Gaining access to internal nodes in a PLD

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Boulder Creek, CA, United States of America

Bryan H Hoyer