International Business Machines Corporation

Bryan Glen Hickerson

John Martin Ludden

John Reysa

Erica Stuecheli

Brian Kozitza

Mohamed Baker Alawieh

David S Levitan

Sheldon Bernard Levenstein

Albert James Van Norstrand, Jr

Michal Rimon

Tuhin Mahmud

Charles Meissner

Avishai Moshe Fedida

Christopher Colletti

Divya Kumudprakash Joshi

Ofer Peled

Brenton Yiu

Elena Tsanko

Craig Atherton

Michael Joseph Schiffli

A computer system, computer readable storage medium, and computer-implemented method for retrograding an instruction stream to enhance random test generation. The method includes generating a test case for a design-under-test (DUT) comprising positioning one or more placeholder instructions in the test case. The method also includes identifying one or more benefiting instructions. The method further includes executing the test case by replacing the one or more placeholder instructions with one or more respective retrograding instructions. The one or more retrograding instructions influence the one or more benefiting instructions.

Instruction stream retrograding to enhance random test generation

Methods and systems for testing a functionality of a code modification operation are described. In an example, a processor can include a processor pipeline comprising one or more execution units. The processor pipeline can execute a first thread. The processor pipeline can further execute a second thread concurrently with the execution of the first thread. The second thread can be executed to modify the first thread using a code modification operation. The processor can further include a test module configured to validate a functionality of the code modification operation based on a result of the modified first thread.

Functional test of processor code modification operations

Methods, systems and computer program products for clustering simulation failures are provided. Aspects include receiving simulation data comprising a plurality of simulation failure files, generating a token for each simulation failure file of the plurality of simulation failure files, determining a token score for each token for each simulation failure file of the plurality simulation failure files, normalizing each token score for each token in the plurality of simulation failure files utilizing a weighting scheme to create a normalized token score for each token, determining a set of groups for the plurality of simulation failure files, and assigning one or more simulation failure files from the plurality of simulation failure files into a group in the set of groups based at least in part on normalized token score.

Clustering simulation failures for triage and debugging

A method, computer program product, and a fail recognition apparatus are disclosed for debugging one or more simulation fails in processor design verification that in one or more embodiments includes determining whether a prediction model exists; retrieving, in response to determining the prediction model exists, the prediction model; predicting one or more bug labels using the prediction model; determining whether a fix is available for the one or more predicted bug labels; and simulating, in response to determining the fix is available for the one or more predicted bug labels, the fix for the one or more predicted bug labels.

Intelligent fail recognition

Blocking instruction fetching in a computer processor, includes: receiving a non-branching instruction to be executed by the computer processor; determining whether executing the non-branching instruction will cause a flush; and responsive to determining that executing the non-branching instruction will cause a flush, disabling instruction fetching for the computer processor for a time, including recoding the instruction such that the recoded instruction will be interpreted by an instruction fetch unit as an unconditional branch instruction.

Blocking instruction fetching in a computer processor

A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.

Generating hardware events via the instruction stream for microprocessor verification

Creating one or more irritator threads on one or more processor cores in a multi-threaded multiprocessor data processing system is provided. A test generator generates non-irritator thread code for execution by a non-irritator thread and irritator thread code for execution by one or more irritator threads of the multi-threaded multiprocessor data processing system. A simulation controller instantiates the non-irritator thread to execute the non-irritator thread code and the one or more irritator threads to execute the irritator thread code. The simulation controller determines if the non-irritator thread has finished execution of the entire instruction stream of the non-irritator thread code. Responsive to the non-irritator thread finishing execution of the entire instruction stream of the non-irritator thread code, the non-irritator thread performs an operation to terminate the execution of the irritator thread code by the one or more irritator threads.

Efficient and self-balancing verification of multi-threaded microprocessors

Growing community of inventors

Cedar Park, TX, United States of America

Bryan Glen Hickerson