Hewlett-packard Company

Hewlett-packard Development Company, L.p.

Bryan G Prouty

Jon L Ashburn

Darel N Emmot

Charles R Dowdell

Roland M Hochmuth

Eric M Rentschler

Robert Paul Martin

Ronald D Larson

Anthony C Barkans

Ian A Elliott

Stuart Yoshida

Kyle R Berry

Alassane Sene

Lawrence G Mahoney

Douglas C Buhler

Steven L Augustine

A method for providing secure access to network secure logical storage partitions is disclosed. The method comprises automatically associating at least one of a plurality of secure logical storage partitions in a storage device in a network with at least one of a plurality of uniquely identified servers in a cell in the network in response to a request for storage over the network. The method also comprises automatically associating the cell with at least one client using network isolation of the cell, and using network isolation of the storage device to restrict access to at least one of the plurality of secure logical storage partitions to the one of the plurality of uniquely identified servers in the cell. In a particular embodiment, the method also comprises determining whether storage capacity is available for the at least one client in response to the request, and automatically creating the cell if the cell does not already exist.

System and method for providing secure access to network logical storage partitions

A method and apparatus for controlling access to a multi-bank memory system. Multiple bank/row activation requests are presented by processes or systems seeking access to the memory. One of the banks of the memory is selected to be the target of a next bank/row activation request. Then, one of the requests corresponding to the chosen bank is selected and issued as the next request. Requests may be conditionally and iteratively selected until one is found whose target row corresponds to a currently active row in the target bank.

Access control system for multi-banked DRAM memory

A buffer facilitates reordering of memory access commands in a memory access command stream so as to create column coherencies that may be exploited with burst-mode memory cycles. A multi-column data storage buffer is provided. Storage control circuitry stores data associated with a memory access command into the multi-column data storage buffer at a column that corresponds to at least one of the LSBs of the column address associated with the memory access command. Flush control circuitry flushes the data storage buffer, when required, in column order. Each entry in the data storage buffer is associated with a unique valid bit. At flush time, the flush control circuitry analyzes the valid bits to determine an appropriate burst type for executing the memory access commands represented by the flushed buffer contents. The flush control circuitry may indicate the determined burst type to memory controller hardware by means of a burst type flag. The data storage buffer may include multiple lines. Each line is associated with one line in a multi-line column address storage buffer. The storage control circuitry stores at least some of the MSBs of the data column addresses in the column address storage buffer. Column address comparison circuitry determines whether at least some of the MSBs of the column address of an incoming memory access command match those currently stored in a line of the column address storage buffer, and if so, select the matching line, but if not, select an unused line.

Creating column coherency for burst building in a memory access command stream

A buffer facilitates reordering of incoming memory access commands so that the memory access commands may be associated automatically according to their row/bank addresses. The storage capacity in the buffer may be dynamically allocated among groups as needed. When the buffer is flushed, groups of memory access commands are selected for flushing whose row/bank addresses are associated, thereby creating page coherency in the flushed memory access commands. Batches of commands may be flushed from the buffer according to a sequence designed to minimize same-bank page changes in frame buffer memory devices. Good candidate groups for flushing may be chosen according to criteria based on the binary bank address for the group, the size of the group, and the age of the group. Groups may be partially flushed. If so, a subsequent flush operation may resume flushing a partially-flushed group when to do so would be more beneficial than flushing a different group chosen solely based on its bank address. The first and last commands flushed in any batch are accompanied by flags indicating that they are the first and last commands in the batch, respectively.

Creating page coherency and improved bank sequencing in a memory access command stream

A modified aggressive precharge method and apparatus for controlling a DRAM or system of DRAMs. Groups of memory access commands are sent to a DRAM controller. A bank/row activate command indicator is associated with the beginning of each group, and a bank precharge command indicator is associated with the end of each group. Normally, the DRAM controller will close the bank/row corresponding to a group responsive to the bank precharge command indicator associated with the end of the group; but the DRAM controller may conditionally leave the bank/row open, as follows: The DRAM controller analyzes the command stream to determine whether first and second groups of memory access commands are directed to the same row and bank. If so, then the precharge command indicated at the end of the first group and the activate command indicated at the beginning of the second group are not executed. The effect is to leave the bank/row of the first group open so that the second group may access it without having to reopen it. Dead time associated with closing and re-opening the same bank/row is eliminated while the advantages of aggressive precharge are maintained.

Modified aggressive precharge DRAM controller

A clear color and count are stored in a frame buffer controller and in a video controller. The image buffer is cleared by writing the clear color into a color bit field and the count into a count bit field of each pixel. For each frame drawn, the count bit field of each pixel modified is updated with the count stored in the frame buffer controller. The counts stored in the frame buffer controller and the video controller are incremented with each new frame. When the counts reach maximum, the process repeats. Each time a pixel is read, the pixel's color bit field is replaced with the stored clear color if the pixel's count bit field is not equal to the stored count. The color bit field and the count bit field may be part of the same word of frame buffer memory. Or, the count value may be stored in an alpha bit field in lieu of an alpha value. If so, each time a pixel is read by the frame buffer controller, the pixel's count bit field may be replaced with a default alpha value stored in the frame buffer controller. Numerous pairs of clear count and clear color registers may be provided in the video controller, each pair corresponding to one window on the display. And numerous pairs of clear count and clear color registers may be provided in the frame buffer controller to better support double buffering and stereo operations.

Technique for reducing the frequency of frame buffer clearing

A method and apparatus for displaying line rotation on a raster computer graphics display, so that substantially rotated versions of original lines maintain a line style pattern that is identical to a line style pattern of the original lines. The invention includes controlling the line style of the substantially rotated version based upon rotation of the substantially rotated version. A line style array is stored in a computer memory for storing consecutive line style pattern features of the substantially rotated version of the first line and assigning a respective length value to each of the pattern features. A line style feature pixel counter is used for counting the pixels of each line style pattern feature. A comparator is used for comparing the incremented pixel counter to the respective length value. A pixel step value is scaled based upon a trigonometric function of the rotation of the substantially rotated version so as to generate a scaled pixel step value. An incrementer is used for incrementing the pixel counter by the scaled pixel step value.

Method and apparatus for raster computer graphics display of rotation

A method and apparatus is provided for interleaving frame buffer controllers in two dimensions. Each frame buffer controller includes an edge stepper, a subspan stepper and a span stepper. The subspan stepper separates each span line into a plurality of parts. Each frame buffer controller provides pixel data for certain parts of the span line. The parts are defined by a start value, a stop value and a starting color value.

System and method for triangle rasterization with frame buffers

A blending system and method for blending source pixel color values with destination pixel color values in a computer graphics system according to a source alpha value includes a resolution increasing circuit that increases a number of bits in the source alpha value to produce an increased resolution source alpha value. Blending hardware implements a blending routine according to a blending equation to blend the source pixel color values with the destination pixel color values using the increased resolution source alpha value. In one embodiment, the resolution increasing circuit includes a squaring circuit that squares the source alpha value.

Computer graphics system with improved blending

A method and apparatus is provided for processing vector primitives with interleaved frame buffer controllers. Each frame buffer controller includes an edge stepper, a span stepper, and a pixel processor. Each edge stepper provides pixel data for multiple pixels during each clock cycle. Any pixels not in an area of the display assigned to a frame buffer controller are discarded without further processing. Pixels which are in the areas assigned the frame buffer controller are further processed. Additionally, two vectors may be processed simultaneaously by the edge steppers.

Multistep vector generation for multiple frame buffer controllers

An apparatus and method for transferring data between first and second circuit blocks of a computer graphics system are provided. The first and second circuit blocks are interconnected by a data bus having n bits. The apparatus includes a circuit in the first circuit block for sequentially transmitting data words from the first circuit block to a second circuit block on the data bus. The data words include one or more long data words having more than n bits. The apparatus further includes a register in the first circuit block for storing bits of the long data words in excess of n bits, and a controller in the first circuit block for loading the bits of the long data words in excess of n bits into the register and for combining the bits of the long data words stored in the register into a composite data word for transmission to the second circuit block. The composite data word may include a short data word having less than n bits. In a preferred embodiment, Z coordinate data words having 40 bits are transmitted with an 8 bit command word over a 32 bit data bus without extra bus cycles.

Data bus protocol for computer graphics system

First next and second next pixel locations are selected simultaneously from among adjacent pixel locations and represent a straight line segment defined by two end locations and having a slope of one or less. An initialization process uses the .DELTA.X and .DELTA.Y of the desired line segment to find various constants, including an initial error term, an error term increment, an error term decrement, an error term double increment, an error term double decrement, and an error term increment-then-decrement. These represent, respectively, an increment in the X location without an increment to the Y location (a step S), an increment in the X location and an increment in the Y location (a jump J), a step followed by a step (two steps SS), two jumps (JJ), and either of a step-then-jump or a jump-then-step (SJ/JS). These five operations correspond to the only possible locations that might be selected, given any starting location. Of the five operations, exactly one of the first two will be for the first next location, while exactly one of the last three will be for the second next location. The present error term is an input to three different adders. Another input to each of the adders is one of the constants for S or J and two of the constants for SS, JJ and SJ/JS. The three additions proceed simultaneously. The initial error term and the resulting three trial error terms can be inspected in relation to error term limits. When the Bresenham Algorithm is implemented, these comparisons are simple determinations of sign. A logic circuit responsive to the error term inspection indicates which combination of the operations S and J correspond to the desired path. A corresponding frame buffer operation code is sent to the a frame buffer address controller. Once the selection is made the error term value for the selected second next pixel location is captured and made to be the error term input for the adders, and the process is ready to select another two pixel locations. If .DELTA.X is an odd number then the second next position is not needed for the final sequence of frame buffer operation codes, and it to be suppressed.

Method and apparatus for simultaneously selecting a plurality of pixels

A system that clears a portion of a graphics display in synchronization with an electron beam scanning the face of the graphics display. When a clear operation for a window on the graphics display screen is received, the system compares the location of the beam with the window and determines whether an interference would occur if the window is cleared immediately. If no interference would occur, the window clear operation is immediately started. If an interference would occur, the system waits until the electron beam has scanned beyond the top of the window before starting the clear operation. Then, before clearing each scan line, the system waits until the beam has already scanned past the scan line being cleared.

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Wellington, CO, United States of America

Bryan G Prouty