Intel Corporation

Bryan E Veal

Annie Foong

Travis T Schluessler

Mazhar I Memon

Steen K Larsen

Daniel S Lake

Sanjeev N Trika

Dan J Williams

Balaji Vembu

Murali Ramadoss

Arun Raghunath

James P Freyensee

Eric R Wehage

In an embodiment, a method includes identifying a core of a multicore processor to which an incoming packet that is received in a packet buffer is to be directed, and if the core is powered down, transmitting a first message to cause the core to be powered up prior to arrival of the incoming packet at a head of the packet buffer. Other embodiments are described and claimed.

Reducing network latency during low power operation

An embodiment of a semiconductor apparatus may include technology to determine one or more logical block addresses for a persistent storage media, determine one or more addresses for a physical memory space, and define a memory-mapped input/output region for the physical memory space with a direct mapping between the one or more addresses for the physical memory space and the one or more logical block addresses for the persistent storage media. Other embodiments are disclosed and claimed.

Memory-addressed maps for persistent storage device

Disclosed are solutions for resolving a redundant array of independent disks (RAID) write hole, or a parity-based fault scenario that occurs when a power failure and a drive failure occur at or close to the same time. Drive array controller logic assigns a sequence number to write operations received from a computing system and converts respective write operations, including corresponding sequence numbers, to a multiple-drive write to a series of RAID drives. A microcontroller at each drive writes, to a history log (HLOG) on the drive, a logical-to-physical address mapping of a prior sector of the drive that was written along with a corresponding sequence number. Upon receipt of a new write to the mapped logical address, the microcontroller removes the HLOG entry for the logical address, and writes a new entry to the HLOG with a new physical address mapping to the logical address with a new sequence number.

Efficient redundant array of independent disks (RAID) write hole solutions

An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

Source core interrupt steering

One embodiment provides a computing device. The computing device includes a processor; a chipset; a memory; and indirection logic. The indirection logic is to receive a host logical block address (LBA) associated with a first sector of data, map the host LBA from a host address space to a first device LBA in a device address space, the device address space related to a non-volatile memory (NVM) storage device physical memory address space, and provide the first sector of data and the first device LBA to the NVM storage device.

Host-managed non-volatile memory

In an embodiment, a storage device may include device processing logic. The device processing logic may acquire a command associated with a key-value pair (KVP). The command may be, for example, a get, set, or delete command. The KVP may include a hash value and an item. The hash value may be a key in the KVP and the item may be a value in the KVP. The device processing logic may translate the acquired command into one or more block-oriented commands which may be executed by the device processing logic to perform various operations on the storage device.

Hash map support in a storage device

Provided are a computer program product, system, and method performing an atomic write operation across multiple storage devices. A determination is made of a plurality of storage devices on which to write data for a write operation. A tag is generated to uniquely identify the write operation. A write command is sent to each of the determined storage devices including the tag and write data to cause each of the storage devices to write the write data at the storage device. Each of the storage devices maintains a copy of a previous version of the data to be updated by the write operation. A revert command is sent with the tag to one of the storage devices to cause the storage device to restore the copy of the previous version of the write data at the storage device.

Performing an atomic write operation across multiple storage devices

Techniques and mechanisms for managing resources of an aggregate device which spans multiple physical devices of a computer platform. In an embodiment, an aggregation device coupled to a host bus of the computer platform receives resource information generated by a pre-boot software process of the computer platform. In another embodiment, the aggregation device, based on the received resource information, represents a resource in a first input/output (I/O) device to a host operating system (OS) as residing in the aggregation device, the first I/O device coupled to the aggregation device via a host bus for exchanging communications referencing a shared address space.

Method, device and system for aggregation of shared address devices

Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.

Method and device to augment volatile memory in a graphics subsystem with non-volatile memory

An embodiment may include circuitry to perform option (a) and/or option (b). In option (a), the circuitry may maintain a journal to record information that is related to a transaction that may result in writing to at least one logical address and at least one physical address of the storage. The information may be recorded in the journal via an atomic operation that may be executed prior to recording, at least in part, the information in a data structure that correlates the at least one logical address to the at least one physical address. In option (b), the circuitry may maintain another data structure that indicates a correlation between at least one other physical address and the at least one logical address. The correlation may be valid prior to completion of the transaction, but the correlation may no longer be valid after the completion.

Maintaining at least one journal and/or at least one data structure by circuitry

Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.

Single instruction processing of network packets

In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed.

A disk array redundancy controller ensures integrity of a mirrored or RAID storage array supporting a host system and minimizes recovery time responsive to a storage volume failure by traversing caches of recently written blocks to identify partially flushed stripes of data and recovering the inconsistent stripes on each of the storage volumes based on a master copy derived from the scan of all pre-failure caches of the storage array. The storage array employs nonvolatile caches in conjunction with solid state drive (SSD) storage volumes, allowing post-failure recovery of recently written blocks. A cache depth at least sufficient to store the largest stripe, or set of blocks, from the host ensures recovery of the entire stripe from a collective scan of the caches of all storage volumes of the storage array.

Method and apparatus for synchronizing storage volumes

A computer system may comprise a plurality of cores that may process the tasks determined by the operating system. A network device may direct a first set of packets to a first core using a flow-spreading technique such as receive side scaling (RSS). However, the operating system may re-provision a task from the first core to a second core to balance the load, for example, on the computer system. The operating system may determine an identifier of the second core using a new data field in the socket calls to track the identifier of the second core. The operating system may provide the identifier of the second core to a network device. The network device may then direct a second set of packets to the second core using the identifier of the second core.

Growing community of inventors

Beaverton, OR, United States of America

Bryan E Veal