Texas Instruments Corporation

Bryan E Bloodworth

Ashish Manjrekar

Echere Iroaga

Paul Merle Emerson

Davy H Choi

Congzhong Huang

Michael Sheperek

Pankaj Pandey

Glenn C Mayfield

Mike Sheperek

Rajarshi Mukhopadhyay

Tuan V Ngo

Hong Jiang

Arup Polley

Jeremy Robert Kuehlwein

Patrick Peter Siniscalchi

Reza Sharifi

Mehedi Hassan

John L Wallberg

Thomas Cougar Van Eaton

Taras Vasylyovych Dudar

James Nodar

Geert A De Veirman

Sen-Jung Wei

Benjamin Sarpong

Nilakantan Seshan

Thomas Cougar VanEaton

Anbu Mani

Aslamali A Rafi

Sankar Sadasivam

Andrija Jezdic

A circuit includes an isolator that provides isolated signal communications between a host-side circuit and a converter-side circuit. The isolated signal communications include a conversion start signal generated in the host-side circuit passing through the isolator to become an isolated conversion start signal in the converter-side circuit. The isolated signal communications includes an isolated system clock generated in the converter-side circuit passing through the isolator to become a system clock in the host-side circuit. A sampling clock generator in the host-side circuit generates the conversion start signal based on the system clock. A logic circuit in the converter-side circuit re-clocks the isolated conversion start signal through the logic circuit.

Circuit to mitigate signal degradation in an isolation circuit

A circuit includes an input that receives a current that increases as a tunneling current sensor moves closer to a media. A high gain path is operatively coupled to the input to amplify the received current as a first amplified output. The first amplified output increases until a saturation threshold is attained for the high gain path. Further increases in the received current beyond the saturation threshold are diverted from the input as an overflow current. A low gain path is operatively coupled to the input to amplify the overflow current as a second amplified output. The second amplified output increases with the overflow current as the tunneling current sensor continues to move closer to the media.

Analog front end for proximity sensing of tunneling current

A current switching system is described. This system includes first and second mirrored devices coupled to each other and a coupled terminal, and the first and second mirrored devices are coupled to an input terminal and an output terminal; a storage element in element in parallel with the first mirrored device and the first degeneration device; a variable impedance device coupled between the coupled terminal and a low voltage device; and a current mirroring accuracy enhancing circuit coupled between the coupled terminal and a high voltage device, wherein the variable impedance device dynamically changes a current at the coupled terminal to a second level depending when a threshold is met, and an impedance on the coupled terminal remains low both before switching and during switching.

Current switching system

Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers are disclosed. A timer in a hard disk drive preamplifier comprises a first switch to selectively store charge in a storage device based on an input signal, the storage device receiving a first current and storing the charge to cause the storage device to have a first voltage that increases at a first rate; a compensation device to cause the first voltage to be substantially equal to a second voltage after a predetermined time period; and a trigger to output a signal when the first voltage is substantially equal to the second voltage, the predetermined time period controlling a transition time between a first hard disk drive operating condition and a second hard disk drive operating condition different than the first operating condition.

Hard disk drive preamplifier timers and methods to calibrate hard disk drive preamplifier timers

An apparatus for use in applying write signals for driving a write head to effect writing information to a memory device; the write signals including a first write signal and a second write signal; includes: (a) a directing circuit receiving the write signals, directing a current to establish a voltage across the write head in a first excursion toward a first polarity in response to the first write signal and directing the current to establish the voltage across the write head in a second excursion toward a second polarity substantially opposite the first polarity in response to the second write signal; (b) a first boost system coupled with the directing circuit and boosting the write voltage toward the first polarity during the first excursion; and (c) a second boost system coupled with the directing circuit and boosting the write voltage toward the second polarity during the second excursion.

Apparatus and method for applying write signals for driving a write head

Managing temperature of a read/write head () in a disk drive system in which there is a power variance due to different operation modes. A circuit device () determines and delivers additional power needed for compensating for the temperature variance due to different operational power requirements. The power is delivered to a resistive heater (Rheat) associated with the head (). The compensating power is based on the delivery voltage, delivery current, and resistance of the resistive heater (Rheat). The delivery current is varied to account for changes in the resistance of the resistive heater (Rheat) since it can vary with temperature. By sensing the current with a sensor (), the resistance is determined via the sensed current and the delivery voltage. The current is adjusted for maintaining the compensating power.

Preamplifier fly height control (FHC) driver and sensing circuit

The present invention discloses an apparatus () comprising a common mode generator circuit () coupled to a current directing circuit adapted to provide current to a first write head connection node () and to a second write head connection node (). The common mode generator circuit () is adapted to provide additional current to the first write head connection node () and to the second write head connection node (), wherein the first write head connection node () is adapted to produce a first write signal, wherein the second write head connection node () is adapted to produce a second write signal, wherein the current and the additional current are adapted to establish a voltage across the first write head connection node () and the second write head connection node (), wherein the voltage is adapted to be pulled toward a first polarity based on the first write signal and toward a second polarity based on the second write signal, and wherein the voltage pulled toward the first polarity and the voltage pulled toward the second polarity are substantially centered about a common mode voltage.

Hard disk drive preamplifier write driver

Disclosed herein are methods and systems for sensing and controlling the temperature of a resistive element configured for use in a read/write head of a magnetic data storage device. In one embodiment, a method includes detecting a voltage across the resistive element, where the voltage varies as a function of a temperature of the resistive element. The method also includes comparing the voltage to a predetermined value to determine a variation of the voltage from the predetermined value, and then altering a power applied to the resistive element based on the variation. In this exemplary embodiment, the temperature of the resistive element is then controlled as a function of the altered applied power.

Temperature compensation systems and methods for use with read/write heads in magnetic storage devices

A fly height controller (FHC;FHC') for controlling the fly height of a read/write head assembly () in a disk drive () is disclosed. A heat element resistor () is disposed within the read/write head assembly (). The fly height controller (FHC;FHC&#x2032;) includes registers (R,W) for storing digital data words corresponding to the desired drive levels to be applied to the heat element resistor () during read and write operations. The registers (R,W) are selectively coupled to a steady-state digital-to-analog converter (DAC) (), depending upon whether a read or write operation is occurring; the output of the steady-state DAC () is applied to a voltage driver (), which in turn drives current into the heat element resistor (). Overdrive and underdrive transistors (P,N) are provided to overdrive and underdrive the input to the voltage driver () in transitions between read and write operations. An initial state register () receives a digital word indicating the desired current for the heat element resistor () when unselected; the output of the initial state register () is applied to an initial state DAC (), which drives an initial state voltage driver (). Control logic (&#x2032;) controls whether the steady-state voltage driver () or initial state voltage driver () drives the heat element resistor (). The fly height controller (FHC&#x2032;) may also be adapted to control the fly height of multiple read/write head assemblies () in a disk drive.

Fly height control for a read/write head in a hard disk drive

The present invention relates to a method of enhancing a preamplifier read recovery in a hard disk drive system and comprises the steps of determining whether the hard disk drive system is transitioning from a non-read state to a read state and initiating a non-read state to a read state transition sequence when a transition from the non-read state to the read state is determined. The transition sequence is independent of a type of non-read state prior to the transitioning. After the non-read state to read state transition sequence is complete the read mode is initiated. In addition, the invention comprises a system for controlling a transition from a non-read state to a read state associated with a preamplifier in a hard disk drive system. The system comprises a detection circuit operable to detect a completion of the non-read state and a non-read state to read state circuit operable to execute a series of events to transition from the non-read state to the read state, wherein the series of events is the same regardless of a type of non-read state. Further, the system comprises a read state initiation circuit operable to initiate the read state after the execution of the series of events.

Preamplifier read recovery parade

A method and circuit for selectively timing amplifier stages of a multi-stage reader amplifier for a hard disk drive system. The reader amplifier includes a first stage, second stage and third stage coupled in series. The method includes the steps of powering the first stage, delaying the enabling of the second stage, and delaying the enabling of the third stage, in order to reduce excursions on the third stage output signal. The circuit includes a logic circuit for successively enabling the second and third amplifier stages.

Relative timing sequence for reader amplifiers

A digital temperature monitor (DTM ( ) includes a proportional-to-absolute temperature (PTAT) sensor ( ) and reference circuit ( ) coupled to the inputs of a comparator ( ). The DTM ( ) monitors the temperature of adjacent and/or proximate integrated circuitry. The method includes the steps of providing a reference signal to the comparator ( ), increasing the reference signal voltage, and determining the temperature of an integrated circuit by determining when the reference signal is greater than the PTAT sensor ( ) output voltage. The DTM ( ) may be implemented as part of a hard-disk drive preamplifier circuit ( ).

Digital temperature monitor

A circuit ( ) and method ( ) for protecting read heads ( ) of a hard-disk drive system ( ). Capacitor C is controllably coupled to a dummy head R during a V mode, so that capacitor C has a low, predictable voltage upon returning to I mode, protecting the read heads ( ) from damage. The circuit ( ) includes logic ( ) and algorithm ( ) determining when to couple the capacitor C to the dummy head R during a servo bank write (SBW) sequence.

Read head protection circuit and method

A preamplifier circuit for a hard disk drive system comprises a preamplifier circuit having a bias voltage circuit stage associated therewith. The preamplifier circuit further comprises a current bias boost recovery circuit operatively coupled to the bias voltage circuit stage which is configured to increase a rate of charging of a noise reduction capacitor associated with the bias voltage circuit stage. A head select boost recovery circuit is also operatively coupled to the bias voltage circuit and is configured to increase a rate of charging or discharging of a bias capacitor associated with the bias voltage circuit stage. Together the circuits allow for a concurrent head switch and current bias switch and avoids the problems associated with the prior art.

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Irving, TX, United States of America

Bryan E Bloodworth