Itt Manufacturing Enterprises, Inc.

Bryan Doi

Richard J Takahashi

Kevin J Osugi

Nhu-Ha Yup

Architecture for embedding a cryptographic engine in a processor is disclosed. An ASIC processor is embedded with a programmable processing core, such as an FPGA, with the key register and I/O registers remaining in fixed logic.

Configurable ASIC-embedded cryptographic processing engine

Memory-based permutation methods and systems are provided for the permutation of data. The memory-based permutation methods and systems provide flexibility and reconfigurability while reducing size and increasing speed. They provide the ability to program a memory, such as a Random Access Memory (RAM), to implement a permutation of source data. The RAM may be reprogrammed to change the permutation pattern thereby providing the flexibility to implement any pattern of permutation from source data to output data and the reconfigurability to change that implementation as desired. Also, the size of the RAM is greatly reduced, and as the input and output data width and number of input and output data bits increase, the size and complexity of the RAM does not increase greatly or exponentially, as with typical conventional systems.

Method and system for reconfigurable memory-based permutation implementation

A mesh of conductors forms a grid in a multi-layered electronic device. The mesh of conductors includes () a first set of conductors disposed in one layer forming parallel lines in the one layer, and () a second set of conductors disposed in another layer forming parallel lines in the other layer. The first set of conductors is configured to provide a first voltage reference, and the second set of conductors is configured to provide a second voltage reference. At least one grid check circuit is coupled to the first set of conductors and the second set of conductors for monitoring presence and/or absence of the first or second voltage references. The parallel lines formed in the one layer and the parallel lines formed in the other layer are substantially perpendicular to each other.

Integrated circuit protection and detection grid

A tamper monitor circuit detects voltage, temperature, and/or clock variations that may be associated with a circuit tampering technique, and triggers an appropriate tamper response. The tamper monitor circuit includes a reference oscillator, a detection oscillator, and a comparison circuit. The reference oscillator supplies a reference signal having a reference frequency. The detection oscillator operates at a circuit temperature and is energized with a supply voltage, and supplies a detection signal having a frequency that varies with variations in the circuit temperature, variations in the supply voltage, or both. The comparison circuit receives the reference signal and the detection signal and, in response to the reference signal, selectively determines the frequency of the detection signal, determines a frequency difference between two or more of the determined frequencies, and supplies a tamper detect signal if the determined frequency difference exceeds a predetermined difference threshold.

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Queen Creek, AZ, United States of America

Bryan Doi