Texas Instruments Corporation

Bryan David Sheffield

Stephen Wayne Spriggs

Theodore Warren Houston

Vikas K Agrawal

George B Jamison

Rashmi Sachan

Suresh Balasubramanian

Xiaowei Deng

Clive D Bittlestone

Sanjive Agarwala

Michael Patrick Clinton

Duy-Loan T Le

Robert L Pitts

Joel J Graber

Eric L Badi

Santhosh Narayanaswamy

Manjeri Krishnan

Brian D Borchers

Roger Griesmer

Mohan Mishra

John David Drummond

Steven P Korson

Doug Counce

Sudhir Kumar Madan

Vinod J Menezes

Joe W McPherson

Theo J Powell

Robert J Landers

David J Toops

Lakshmikantha V Holla

George Ernest Harris

Tam Minh Tran

Nisha Padattil Kuliyampattil

Stephen K Barna

Kun-His Li

Rengarajan S Krishnan

Mark J Jensen

Kun-Hsi Li

Dwayne Ward

Roger C Griesmer

The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode control circuitry coupled to the array and configured to alter a supply voltage level to the SRAM array based on a mode of operation. The circuitry also includes control inputs coupled to the mode control circuitry for selecting one of the low power write mode, the full active mode, and optionally a retention mode of operation. The mode control circuitry is configured to receive the control inputs to select one of the three modes of operation, and to alter one or more supply voltage levels to the array, for example, the Vss supply voltage using a Vss supply circuit and the Vdd supply voltage using a Vdd supply circuit, based on the selected mode of operation. The mode control circuitry may also comprise a bitline precharge circuit configured to alter a bitline precharge voltage.

Memory with low power mode for write

The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.

Contact fuse which does not touch a metal layer

Memory with low power mode for WRITE

A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. During debug mode, where the individual array cells do not participate in search, all the cells in the debug column behave the same way to emulate a match/mismatch on all words. The circuit provides a control input to include address evaluation of a debug cell in a row. The circuit also provides simultaneous switching noise analysis on an evaluating row. The resulting CAM cell provides a circuit to test individual rows for defects and noise analysis.

Match mismatch emulation scheme for an addressed location in a CAM

A technique that provides width expansion of two CAMs of varying widths by combining match results from two CAMs by integrating the two CAMs. In one embodiment, a synchronizer circuit triggers the operation of an External Priority Encoder module which can be used to cascade two CAMs to form a wider CAM. When the External Priority Encoder module is used with the CAM, the External Priority Encoder module will receive MATCH signals and control signals from individual CAMs residing on either side, and will be triggered by the last arriving signal between two ports associated with two CAMs. In case one of the ports is disabled the External Priority Encoder module relies totally on the control signal from the other port for operation. The synchronizer circuit has the ability to handle mismatches between the CAMs as well as differentiating valid and invalid combinations between the CAMs.

Technique for CAM width expansion using an external priority encoder

Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes. Accordingly, the CAM can be debugged to isolate memory failures from priority encoder failures, which significantly reduces the need for design changes. The present invention provides the ability to test the CAM functions very efficiently, thereby reducing the test time.

CAM test structures and methods therefor

A dual port memory implemented using a single port memory core. In an embodiment, the access requests from the two ports are processed in a single memory clock cycle. In one implementation, the access request corresponding to the first port is processed in the high logic state of the memory clock cycle, and the access request corresponding to the second port is processed in the low logic state of the memory clock cycle. A single port memory core may provide multiple memory enable signals and corresponding strobe signals, with each combination of memory enable signal and strobe signal facilitating the memory access request from a corresponding port. An alternative embodiment uses the duration of each clock cycle of the memory clock signal more efficiently by starting the second memory access soon after completion of the first memory access (without waiting for the logic low of memory clock signal).

Dual port memory unit using a single port memory core

The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device () according to the present invention has a row () of memory cells and driver circuitry () preceding the row of memory cells. The present invention provides an intervention circuit () instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry () preceding the intervention circuit is powered down.

System for reducing row periphery power consumption in memory devices

A novel array fault testing for a TCAM system that includes a plurality of TCAM blocks that is organized into at least one rectangular array having rows each having a plurality of TCAM blocks, a group of TCAM cells and associated read/write bit lines connecting the group of TCAM cells to write driver and decoding block. The data decode bypass circuit of the TCAM cell provides a raw write feature to detect faults in a full suite of memory related tests. The debug input of the data debug bypass circuit of the TCAM cell when asserted in the test mode enables the TCAM cell to write raw, unencoded data into the array, and when deasserted in the test mode, enables the testing of the TCAM array. The resulting TCAM cell provides exhaustive fault testing thereby detecting and eliminating faults in TCAM.

Array fault testing approach for TCAMs

A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Self-clocking memory device

An amplifier circuit includes an amplifier section (), an equalization section (), and an activation section (). The P-channel transistors () of the amplifier section are coupled to a supply terminal (). The N-channel transistors () of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (), respectively. In the activation section, first and second pull down transistors () are coupled between the first and second input terminals, respectively, and a second power supply terminal (), and third pull down transistor between the first and second input terminals. The control gates of the first, second and third pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.

Stable source-coupled sense amplifier

Method of operating a memory at high speed using a cycle ready status output signal

A technique to enhance performance and reduce silicon area for a TCAM system which includes a plurality of CAM blocks that are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of TCAM cells and associated read/write bit lines connecting the group of CAM cells to search bit lines. Each TCAM cell in the TCAM architecture includes a pair of memory elements that is connected to a pair of associated compare circuits such that the interconnections between the memory elements and the compare circuits are substantially vertical in active MOS layers and substantially horizontal in the metal layers to facilitate sharing of adjacent cells thereby providing reduced silicon area and a short aspect ratio.

High performance and reduced area architecture for a fully parallel search of a TCAM cell

Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.

Electrical fuse control of memory slowdown

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McKinney, TX, United States of America

Bryan David Sheffield