Freescale Semiconductor,inc.

Hewlett-packard Company

Samsung Electronics Co., Ltd.

Hewlett-packard Development Company, L.p.

Motorola Corporation

Mercury Computer Systems, Inc.

Convex Computer Corporation

Other

Nxp Usa, Inc.

Mercury Computer Systemc, Inc.

Bryan D Marietta

Bryan D Hornung

Daniel L Bouvier

David B Kramer

Gary L Whisenhunt

Kumar K Gala

Robert C Frisch

Douglas A Oppedahl

Robert K King

Michael D Snyder

Peter Jeremy Wilson

Joseph Gergen

David W Todd

James F Wenzel

Robert Keith DeHaven

Craig C Hunter

Michael C Becker

James Patrick Johnston

Benjamin Charles Eckermann

Gregory B Shippen

Laura Weber

David C Holloway

According to one general aspect, an apparatus may include a memory configured to store both data and metadata, such that for portions of data associated with the metadata, the data and metadata are interleaved such that a unit of metadata succeeds each power of two contiguous units of data. The apparatus may also include a memory manager circuit. The memory management circuit may be configured to receive a data access to the memory, wherein the data access includes a public memory address. The memory management circuit may be configured to determine if the public memory address is associated with metadata. The memory management circuit may be configured to, if so, convert the public memory address to a private memory address. The memory management circuit may be configured to complete the data access at the private memory address.

Apparatus to insert error-correcting coding (ECC) information as data within dynamic random access memory (DRAM)

A system and methods controlling wake events in a data processing system is described. A broadcast wake-up signal staggering order is determined in response to a first wake event. A staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the broadcast wake-up signal staggering order. The broadcast wake-up signal staggering order is changed in response to a second wake event. And a changed staggered broadcast wake-up signal is distributed to a plurality of processing elements based on the changed broadcast wake-up signal staggering order.

Method and apparatus for controlling wake events in a data processing system

A method and circuit for a data processing system () provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers (-) located at the processor core () to enable quick and efficient interrupt priority blocking on a partition basis.

Interrupt priority management using partition-based priority blocking processor registers

A method and circuit for a data processing system () provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers (-) located at the processor core () to enable quick and efficient interrupt priority blocking on a partition basis.

Processor interrupt interface with interrupt partitioning and virtualization enhancements

A method and circuit for a data processing system provide virtualized instructions for accessing a partitioned device (e.g.,) by executing a control instruction () to encode and store an access command (CMD) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register () at a physical address (PA) retrieved from a special purpose register () so that the partitioned device () can determine if the access command can be performed based on local access control information.

Virtualized instruction extensions for system partitioning

A method and circuit for a data processing system provide a partitioned interrupt controller with an efficient deferral mechanism for processing partitioned interrupt requests by executing a control instruction to encode and store a delay command (e.g., DEFER or SUSPEND) in a data payload with a hardware-inserted partition attribute (LPID) for storage to a command register () at a physical address (PA) retrieved from a special purpose register () so that the partitioned interrupt controller () can determine if the delay command can be performed based on local access control information.

Virtualized interrupt delay mechanism

A method and circuit for a data processing system () provide a virtualized programmable interrupt control system () which processes interrupt event reports from interrupt sources (e.g.,) which generate write transactions to an address for an interrupt event register () which is authenticated and then interpreted based on the current state of the targeted interrupt to generate the next state using an interpretation table () and predetermined configuration/state bits (-).

Write transaction interpretation for interrupt assertion

In a data processing system having a plurality of resources and plurality of partitions, each partition including one or more resources of the plurality of resources, a method includes receiving an access request to a target resource of the plurality of resources; using a first set of transaction attributes of the access request to determine a partition identifier for the access request in which the partition identifier indicates a partition of the plurality of partitions which includes the target resource; using the partition identifier to determine access permissions for the partition indicated by the partition identifier; and based on the access permissions, determining whether or not the access request is permitted.

Method and apparatus for determining access permissions in a partitioned data processing system

A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.

Interrupt controller for accelerated interrupt handling in a data processing system and method thereof

A SCI controller manages responses and requests between SCI interconnection rings and memory access controllers. The SCI controller includes a request activation queue that stores information about the requests until the SCI rings have the resources to handle the requests. The controller also has a response activation queue that stores information about the responses until the memory access controller is accessible. The queues do not store the request and response packets, but rather store information that is used to construct the request and response packets. The SCI controller also has a contents addressable memory or CAM that checks for an address match between the current requests and responses and previous requests and responses. A table stores more specific information about the previous requests.

Using local storage to handle multiple outstanding requests in a SCI system

A digital data system employs multiple error protection mechanisms on messages that pass along a link interconnect fabric from one node or device to another node or device. The nodes may be end points (such as processor or storage units), or may be intermediate devices or branch points (such as routers or switches in the interconnect fabric). The interconnect fabric comprises a set of one or more routers, switches, electrical, optical, electroptical or other links along which messages are passed. Messages are packets having a defined format including, e.g., a header portion, typically with source and target addresses, and codes indicating message-type or other information, followed by one or more data or other fields. A first node ('sending' node) of a digital data system as described sends a data transmission comprising one or more message packets to a second node ('receiving' node) over a link of a fabric as described above. The receiving node returns a control symbol to the sending node for each packet received on the link. The sender uses information in that symbol to control the further transmission of message packets to receiver over the link.

Method and system for link fabric error detection and message flow control

A digital data system comprises a plurality of links for passing messages between nodes, which may be end points such as memory or processing units, or intermediate or branch points such as routers or other devices in the system. A link level flow control is implemented by control symbols passed between adjacent nodes on a link to efficiently regulate message burden on the link. The control symbols may be embedded within in a message packet to quickly effect control on a link&#x2014;such as reducing data flow, requesting retransmission of corrupted data, or other intervention&#x2014;without disruption of the ongoing packet reception. A control symbol may be recognized within the packet by a flag bit, a marker such as a transition in a signal, or a combination of characteristics. The control symbol may be a short word, having a control action identifier code at defined bit positions to indicate the desired link-level control function. A node receiving the control symbol implements the designated control action while maintaining packet order data (such a bit positions and byte counts), and applying message housekeeping processing (such as error checking) as though the control symbol were absent. The control symbol is thus embedded in a manner such that a receiving node need not receive a complete message, or even a complete packet, before acting on the control symbol. The beginning and end of the interrupted packet, meanwhile, are handled as a single message packet, and are processed by the receiving node in properly-aligned bit positions, allowing message flow to continue along the link without interruption. Thus, retransmission of the affected packet or message is not required. The result is that control operations dictated by the embedded control symbol are effected immediately and without slowing down communications.

Digital data system with link level message flow control

A data communication system () has a plurality of devices () which communicate by transmitting information packets having order tags which are processed by an input unit () and an output unit () in each device. A packet is sent from a transmitting device to a receiving device having an ordering tag wherein both devices are initially order synchronized by starting with the same ordering tag value. Packet transmissions are forced to occur in an order which follows a predetermined ordering of order values which the ordering tags can have. If the receiving device does not receive a packet having the correct order tag value or if a transmission error is detected, the receiving device tells the transmitting device to resend the packet. Any subsequent outstanding transmissions are discarded. Packet ordering and verification occurs at each device-to-device connection.

Method and apparatus for maintaining packet ordering with error recovery among multiple outstanding packets between two devices

A multi-processing system ( ) comprises a plurality of groups, each having an arbitrary number of processing systems ( ). Memory coherency may or may not be established within any particular group. However, each group is intentionally arranged by functionality so that memory coherency, if implemented, only needs to be maintained within the group. Information transfers between two groups are therefore non-coherent by definition. Memory coherency implementation is significantly reduced in the system. A transaction format utilizes group and processing system identifiers to implement the simplified coherency scheme.

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Austin, TX, United States of America

Bryan D Marietta