Micron Technology Incorporated

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Bryan D Hornung

Tony M Brewer

David M Patrick

Douglas John Vanesko

Bryan D Marietta

Gregory S Palmer

Paul F Vogel

Patrick Alan Estep

Dean E Walker

Keith W Shaw

Christopher A Baronne

Robert K King

Gary Belgrave Gostin

Mark Edward Shaw

Michael L Ziegler

Michael Grassi

Erin Antony Handgen

Skyler Arron Windh

Craig Lawrence Warner

Joseph F Orth

Michael Joseph Phelps

Chris M Giles

Michael K Traynor

Lionel Bening

Robert Pflederer

A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I/O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command/address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I/O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.

Multiple channel memory system

Methods, systems, and devices for shared virtual address spaces are described. In some examples, a globally shared address space may be shared across a plurality of memory devices that are included in one or more domains. A host system may set parameters for determining whether an address (e.g., a virtual address) is included within the globally shared address space, and whether the address is associated with a memory device. When a memory device receives a memory request (e.g., a data packet), a processing unit of the memory device may determine whether an address included in the memory request is associated with the memory device. The processing unit may either initiate an access operation on a physical address of the memory device or transmit the memory request to another memory device.

Shared virtual address spaces

Various examples are directed to systems and methods for performing operations in a reconfigurable compute fabric. A dispatch interface may send a first asynchronous message to a first flow controller of a first synchronous flow. The first asynchronous message may instruct the first flow controller to begin execution of a first-level loop. The first synchronous flow may send a second asynchronous message to a second flow controller of a second synchronous flow. The second asynchronous message may instruct the second flow controller to execute a second-level loop. The first flow controller may receive a third asynchronous message indicating that the second-level loop has completed and that a synchronous flow thread is free for executing a next iteration of the first-level loop.

Loop execution in a reconfigurable compute fabric

Methods, systems, and devices for virtual addresses for a memory system are described. In some examples, a virtual address space may be shared across a plurality of memory devices that are included in one or more domains. The memory devices may be able to communicate with each other directly. For example, a first memory device may be configured to generate a data packet that includes an identifier and an address that is included in the shared virtual address space. The data packet may be transmitted to a second memory device based on the identifier, and the second memory device may access a physical address based on the address.

Virtual addresses for a memory system

A reconfigurable compute fabric can include multiple nodes, and each node can include multiple tiles with respective processing and storage elements. The tiles can be arranged in an array or grid and can be communicatively coupled. In an example, the tiles can be arranged in a one-dimensional array and each tile can be coupled to its respective adjacent neighbor tiles using a direct bus coupling. Each tile can be further coupled to at least one non-adjacent neighbor tile that is one tile, or device space, away using a passthrough bus. The passthrough bus can extend through intervening tiles.

Connectivity in coarse grained reconfigurable architecture

Devices and techniques for handling breakpoints in a multi-element processor are described herein. A compute node includes a hybrid threading processor and hybrid threading fabric, where the hybrid threading fabric comprises a plurality of memory-compute tiles, where each of the memory-compute tiles include respective processing and storage elements used to execute a kernel, and where each of the memory-compute tiles includes a breakpoint controller to initiate a breakpoint for the plurality of memory-compute tiles.

Mechanism to handle breakpoints in a multi-element processor

Linear interpolation is performed within a memory system. The memory system receives a floating-point point index into an integer-indexed memory array. The memory system accesses the two values of the two adjacent integer indices, performs the linear interpolation, and provides the resulting interpolated value. In many system architectures, the critical limitation on system performance is the data transfer rate between memory and processing elements. Accordingly, reducing the amount of data transferred improves overall system performance and reduces power consumption.

Interpolation acceleration in a processor memory interface

Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which solve the above problems using a global shared region of memory that combines memory segments from multiple CXL devices. Each memory segment is a same size and naturally aligned in its own physical address space. The global shared region is contiguous and naturally aligned in the virtual address space. By organizing this global shared region in this manner, a series of three tables may be used to quickly translate a virtual address in the global shared region to a physical address. This prevents TLB thrashing and improves performance of the computing system.

Global virtual address space across operating system domains

Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allows an application of a computer system to create a series of one or more logs of writes to one or more memory locations of a memory device. The logs may comprise the values at the end of the log interval of the one or more memory locations that were written to during a log interval. In some examples, the logs do not include intermediate writes to the one or more memory locations (only the final value) and do not include values of memory locations that were not written to during the interval. After an event, software can apply these logs to a copy of the original memory region state to recover the contents of the locations at any of the logged points. These logs may be useful to recreate the state of the memory at various points during the application's execution.

Method for providing logging for persistent memory

Devices and techniques for loading contexts in a coarse-grained reconfigurable array processor are described herein. A system or apparatus may include context load circuitry operable to load context for a coarse-grained reconfigurable array processor, where the context load circuitry is configured to: (a) receive a kernel identifier; (b) access a first registry to obtain a context mask base address; (c) determine a context mask address from the context mask base address and the kernel identifier; (d) access a second registry to obtain a context state base address; (e) determine a context state address from the context state base address and the kernel identifier; (f) use a context mask at the context mask address to determine corresponding active context state; and (g) load the corresponding active context state into the coarse-grained reconfigurable array processor.

Context load mechanism in a coarse-grained reconfigurable array processor

Various examples are directed to systems and methods for executing a loop in a reconfigurable compute fabric. A first flow controller may initiate a first thread at a first synchronous flow to execute a first portion of a first iteration of the loop. A second flow controller may receive a first asynchronous message instructing the second flow controller to initiate a first thread at a second synchronous flow to execute a second portion of the first iteration. The second flow controller may determine that the first iteration of the loop is the last iteration of the loop to be executed and initiate the first thread at the second synchronous flow with a last iteration flag set.

Loop execution in a reconfigurable compute fabric using flow controllers for respective synchronous flows

Disclosed in some examples are methods, systems, and machine readable mediums that provide increased bandwidth caches to process requests more efficiently for more than a single address at a time. This increased bandwidth allows for multiple cache operations to be performed in parallel. In some examples, to achieve this bandwidth increase, multiple copies of the hit logic are used in conjunction with dividing the cache into two or more segments with each segment storing values from different addresses. In some examples, the hit logic may detect hits for each segment. That is, the hit logic does not correspond to a particular cache segment. Each address value may be serviced by any of the plurality of hit logic units.

High bandwidth gather cache

A synthetic-aperture radar (SAR) antenna emits radar pulses and receives their reflections. SAR is typically used on a moving platform, such as an aircraft, drone, or spacecraft. Since the position of the antenna changes between the time of emitting a radar pulse and receiving the reflection of the pulse, the synthetic aperture of the radar is increased, giving greater accuracy for a same (physical) sized radar over conventional beam-scanning radar. The pulse data is processed, using a backprojection algorithm, to generate a two-dimensional image that can be used for navigation. The order in which the SAR data is processed can impact the likelihood of cache hits in accessing the data. Since accessing data from cache instead of memory storage reduces both access time and power consumption, devices that access more data from cache have greater battery life and range.

Increasing cache hits for synthetic aperture radar

A dispatch element interfaces with a host processor and dispatches threads to one or more tiles of a hybrid threading fabric. Data structures in memory to be used by a tile may be identified by a starting address and a size, included as parameters provided by the host. The dispatch element sends a command to a memory interface to transfer the identified data to the tile that will use the data. Thus, when the tile begins processing the thread, the data is already available in local memory of the tile and does not need to be accessed from the memory controller. Data may be transferred by the dispatch element while the tile is performing operations for another thread, increasing the percentage of operations performed by the tile that are performing useful work and reducing the percentage that are merely retrieving data.

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Plano, TX, United States of America

Bryan D Hornung