Vlsi Technology, Inc.

Bryan C Doi

Vincent J Coli

Steven D Thomas

Vito D Giglio

A method for making an integrated circuit characterized by: determining a range of bonding pad pitches which varies between a minimum bonding pad pitch and a maximum bonding pad pitch; setting a driver pitch to the minimum bonding pad pitch; forming a base set including a plurality of drivers having the determined driver pitch; forming customization layers over the base set, where the customization layers include a plurality of bonding pads having a pad pitch greater than the minimum bonding pad pitch but less than or equal to the maximum bonding pad pitch; and coupling some, but not all, of the drivers to the pads. As a result, a single base set can be used to make integrated circuits having a range of bonding pad pitches. The method and structure of the present invention are very well adapted for use in gate array integrated circuits.

Integrated circuit with variable pad pitch

A method is used to shield a data line in a first metal layer from electrical probe. A first shielding line is placed directly over the data line. The first shielding line is within a second metal layer which is above the first metal layer. In the preferred embodiment, a second shielding line is placed on a first side of the data line. The second shielding line is in the first metal layer. Also, a third shielding line is placed on a second side of the data line. The third shielding line is also in the first metal layer. Also in the preferred embodiment, the first shielding line, the second shielding line and the third shielding line are all connected to Vss.

Security circuitry with select line and data line shielding

A security system is used for programmable read-only memory locations within a very large scale integrated (VLSI) circuit. In a first security bit memory location there is stored a first security data bit. The first security data bit has a first value when the first security bit memory location is unprogrammed and a second value when the first security bit memory location is programmed. In a second security bit memory location there is stored a second security data bit. The second security data bit has the first value when the second security bit memory location is unprogrammed and the second value when the second security bit memory location is programmed. A selection logic is electrically coupled to the first security bit memory location and the second security bit memory location. The selection logic selects no security data bit, the first security data bit or the second security data bit to be used to generate a security access signal. An access logic allows and prevents direct access, by any device outside the VLSI circuit, to the programmable read-only memory locations in response to the security access signal. The access logic prevents any device outside the VLSI circuit direct access to the programmable read-only memory locations when the selection logic selects no security data bit, when the selection logic selects the first security bit and the first security data bit has the second value, or when the selection logic selects the second security bit and the second security data bit has the second value.

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Fremont, CA, United States of America

Bryan C Doi