Renesas Technology Corp.

Hitachi, Ltd.

Visualize K.k.

Bryan Atwood

Takao Watanabe

Takeshi Sakata

Kazumasa Yanagisawa

Kazuo Yano

Tomoyuki Ishii

Taro Osabe

Masashi Takada

Hiroshi Tanaka

Takanobu Tsunoda

Subas Chhatkuli

Jin Koh

A method includes receiving from a camera a 2D front-view digital image (FDI) and side-view digital image (SDI) of a human body; receiving one or more camera parameters (CPs); executing a front depth-estimation model (DEM) generated through pre-training a first machine-learning model (MLM) to convert the FDI and SDI into a front depth map (DM) and side DM, respectively; executing a rear DEM generated through pre-training a second MLM to estimate a rear DM based on the FDI, SDI, and front and side DMs; combining the front and rear DMs to generate a 3D model; executing a front key-point (FKP) estimation model generated through pre-training a third MLM to estimate one or more FKPs; and extracting a body measurement based on the 3D model and FKPs, the first and second MLMs each including a respective encoder and decoder, each respective decoder configured to be executed based on the CPs.

Self-implementing accurate body measurements by a user using a mobile device

There is provided at least one processor block including a plurality of load store interfaces (), a plurality of memory banks (), an input/output port having at least one of an input port () and an output port (), and a crossbar switch (), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.

Data processor with internal memory structure for processing stream data

A semiconductor device capable of accessing to the memory with a high speed, and including a memory with a large capacity. The semiconductor device includes a plurality of memory banks (Bank)towhere the write cycle time is twice as long as the read cycle and each provided with the separate write and read ports, and two cache data banks CDand CD, in which, for example, in the case that an external write instruction with continuous cycles is issued in cycle #, the data of Bankstored in CD, Rowcannot be written back since Bankis busy with the cycle #, the data of Bankstored in CD, Rowcan be written back instead.

Semiconductor device

An apparatus is to reduce, during the standby time, the electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are connected, and a switch is provided between the source electrode and a power supply terminal. The leakage current during the standby time is interrupted by bringing the switch into a conducting state during the active time, and by bringing the switch into a nonconducting state during the standby time.

Semiconductor integrated circuit

A semiconductor device capable of accessing to the memory with a high speed, and comprising a memory with a large capacity. The semiconductor device comprises a plurality of memory banks (Bank)towhere the write cycle time is twice as long as the read cycle and each provided with the separate write and read ports, and two cache data banks CDand CD, in which, for example, in the case that an external write instruction with continuous cycles is issued in cycle #, the data of Bankstored in CD, Rowcannot be written back since Bankis busy with the cycle #, the data of Bankstored in CD, Rowcan be written back instead.

An apparatus and method to reduce, during standby time, electric power caused by the leakage current flowing through a storage transistor in a 3-transistor dynamic cell. Source electrodes of storage transistors in a plurality of 3-transistor dynamic cells constituting a memory array are connected, and a switch is provided between the source electrode and a power supply terminal. The leakage current during the standby time is interrupted by bringing the switch into a conducting state during the active time, and by bringing the switch into a nonconducting state during the standby time.

A high capacity, fast access dynamic random access memory is provided. Furthermore, a pipelined write method can be realized at each array block by affixing a latch between the sense amplifier and write data line for each column. In this manner, a data write phase can occur simultaneously with the pre-read phase of the following address. Using this method, the effective access speed to the array block can be increased, yielding a fast access cache memory.

Semiconductor memory pipeline buffer

A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

Semiconductor memories

A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two- and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

Growing community of inventors

Tokyo, Japan

Bryan Atwood