Silicon Storage Technology, Inc.

Atmel Rousset S.a.s.

Laas-cnrs

Laas-cnre

Bruno Villard

Nhan Do

Jinho Kim

Catherine Decobert

Yuri Tkachev

Parviz Ghazavi

Gilles Festes

Bernard Bertello

Elizabeth Cuevas

Thierry Pedron

Jean Francois Thiery

Willem-Jan Toren

Elsa Hugonnard-Bruyere

Gaetan Toulon

Frederic Morancho

Ignasi Cortes Mayol

Serguei Jourba

Fan Luo

Cynthia Fung

Latt Tee

A method of testing non-volatile memory cells formed on a die includes erasing the memory cells and performing a first read operation to determine a lowest read current RCfor the memory cells and a first number Nof the memory cells having the lowest read current RC. A second read operation is performed to determine a second number Nof the memory cells having a read current not exceeding a target read current RC. The target read current RCis equal to the lowest read current RCplus a predetermined current value. The die is determined to be acceptable if the second number Nis determined to exceed the first number Nplus a predetermined number. The die is determined to be defective if the second number Nis determined not to exceed the first number Nplus the predetermined number.

Method of determining defective die containing non-volatile memory cells

A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

Method of forming split gate memory cells with thinned side edge tunnel oxide

A method of forming a memory device includes forming a floating gate on a memory cell area of a semiconductor substrate, having an upper surface terminating in an edge. An oxide layer is formed having first and second portions extending along the logic and memory cell regions of the substrate surface, respectively, and a third portion extending along the floating gate edge. A non-conformal layer is formed having a first, second and third portions covering the oxide layer first, second and third portions, respectively. An etch removes the non-conformal layer third portion, and thins but does not entirely remove the non-conformal layer first and second portions. An etch reduces the thickness of the oxide layer third portion. After removing the non-conformal layer first and second portions, a control gate is formed on the oxide layer second portion and a logic gate is formed on the oxide layer first portion.

Method of forming split gate memory cells with thinned tunnel oxide

A p-channel LDMOS device with a controlled n-type buried layer (NBL) is disclosed. A Shallow Trench Isolation (STI) oxidation is defined, partially or totally covering the drift region length. The NBL layer, which can be defined with the p-well mask, connects to the n-well diffusion, thus providing an evacuation path for electrons generated by impact ionization. High immunity to the Kirk effect is also achieved, resulting in a significantly improved safe-operating-area (SOA). The addition of the NBL deep inside the drift region supports a space-charge depletion region which increases the RESURF effectiveness, thus improving BV. An optimum NBL implanted dose can be set to ensure fully compensated charge balance among n and p doping in the drift region (charge balance conditions). The p-well implanted dose can be further increased to maintain a charge balance, which leads to an Rdson reduction.

Enhanced HVPMOS

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Aix en Provence, France

Bruno Villard