Keyssa Systems, Inc.

Ensphere Solutions, Inc.

Sumitomo Electric Industries, Limited

Bruno Tourette

Jerome Jean Ribo

Hessam Mohajeri

Roger Dwain Isaac

Pavan Kumar Hanumolu

Emad Afifi

A device comprises a clock data recovery (CDR) circuit. The CDR circuit has an input node to receive an input data signal, an output node, a data recovery circuit, and a self-test circuit. The CDR circuit supports a first mode of operation and a second mode of operation. In the first mode, the CDR circuit receives the input data signal at the input node and provides the input data signal to an input of the data recovery circuit, the data recovery circuit recovers first data from the input data signal, and the CDR circuit provides the first data for output at the output node. In the second mode, the self-test circuit generates a test data pattern which is provided to the output node and looped back to the input of the data recovery circuit, the data recovery circuit recovers second data from the test data pattern, and the self-test circuit checks the second data for errors.

Testing of clock and data recovery circuits

Methods, systems, and apparatus for inserting a re-timer signal between a transmitter and a receiver, including receiving, from the transmitter, an input data signal having encoded words, where each encoded word of the encoded words has a word length of a predetermined number of bits; generating, by a re-timer and based on the input data signal, a regenerated clock signal and an output data signal; determining, based on the regenerated clock signal, a timing difference between the input data signal and the output data signal of the re-timer; and applying, by the re-timer and based on the timing difference between the input data signal and the output data signal, a delay to the input data signal to generate a delayed output data signal, such that a timing difference between the input data signal and the delayed output data signal corresponds to N word lengths.

Re-timer network insertion

Systems, methods, and apparatus for generating a clock signal using re-timer circuitry, including receiving an input data signal transmitted without a reference clock signal; comparing the input data signal with a re-timer clock signal to determine a frequency difference between the input data signal and the re-timer clock signal; determining a data rate of the input data signal based on the frequency difference between the input data signal and the re-timer clock signal; and generating, based on the data rate of the input data signal, a control signal for adjusting a frequency of the re-timer clock signal to frequency-lock the re-timer clock signal with the input data signal.

Multi-data rates multi-protocol communications techniques for reference-less re-timer

Systems, methods, and apparatus for regenerating a data signal and a clock signal are provided. One of the apparatuses include clock regeneration loop circuitry configured to receive an input data signal transmitted without a reference clock signal, and to generate an output reference clock signal having an adjustable clock frequency that substantially matches a data rate of the input data signal; data detection loop circuitry configured to generate a phase offset control signal for adjusting a phase of a clock signal that samples the input data signal, and to generate, based on the phase offset control signal, a sampled input data signal; and an elastic buffer configured to generate, based on the output reference clock signal and the sampled input data signal, an output data signal that substantially aligns with the output reference clock signal, and enable the different adaptation dynamic of the loops.

Multi-protocols and multi-data rates communications

The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Phase locked loop circuit

The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.

Wide band clock data recovery

Low jitter clock generator for multiple lanes high speed data transmitter

A current mirror circuit and an optical receiver circuit implementing with the current mirror circuit are disclosed. The current mirror circuit provides two MOSFETs and two differential amplifiers. The MOSFETs are operated under the same bias condition even the power supply voltage decreases due to the virtual short-circuit characteristic between two inputs of the differential amplifier. One of the differential amplifiers provides a variable gain and output impedance characteristic to stabilize the feedback loop formed by this differential amplifier and one of the MOSFETs.

Growing community of inventors

Cupertino, CA, United States of America

Bruno Tourette