National Semiconductor Corporation

Zilog, Inc.

Bruno Kranzen

Dragan Maksimovic

Sandeep Dhar

Ravindra Ambatipudi

Luan Minh Vu

Kamal Rajkanan

Jonathan Robert Knight

Larry Bradley

A voltage regulation and battery charging system is provided. The system may include a switching regulator selection control circuit, two switching regulator controller circuits, two power transistors, a common synchronous transistor, a common LC circuit, and a battery charger circuit. The two switching regulator controller circuits may synchronously switch the two power transistors and the one common synchronous transistor. One of the switching regulator controller circuits may receive voltage from an AC adapter and the other may receive voltage from the battery. The first switching regulator controller circuit is employed to provide system power when the AC adapter is connected. When the battery is used to provide the system power, the second switching regulator controller circuit is used to down-convert the battery voltage to provide the system power.

Apparatus and method for magnetic charger IC for batteries with recycling of the LC filter for re-use as a battery step-down converter

A voltage regulation and battery charging system is provided. The system may include a switching regulator selection control circuit, two switching regulator controller circuits, two power transistors, a common synchronous transistor, and a common LC circuit. The two switching regulator controller circuits may synchronously switch the two power transistors and the one common synchronous transistor. One of the switching regulator controller circuits may receive a voltage from an AC adapter and the other may receive a voltage from a USB port. Further, the switching regulation selection control circuit selects which of the two switching regulator controller circuits controls the regulation of the system output voltage employing the common LC filter.

Apparatus and method for dual source, single inductor magnetic battery charger

There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum delay time of a critical path in the digital processing component is determined by a level of a power supply, VDD, of the digital processing component. The adjustable power supply is capable of supplying VDD to the digital processing component. The power supply adjustment circuitry is operable to receive a first selected clock signal and adjusts the level of VDD such that the maximum delay time of the critical path of the digital processing component is less than a pulse-width duration between a first clock edge of the first selected clock signal and a second clock edge of the first selected clock signal immediately following the first clock edge.

Adaptive voltage scaling digital processing component and method of operating the same

There is disclosed an adaptive voltage power supply that finely adjusts VDD to an optimum level. The adaptive voltage power supply comprises: 1) a first charging circuit capable of increasing a reference voltage on a charge capacitor in response to receipt of a first VDD control signal; 2) a second charging circuit capable of decreasing the reference voltage on the charge capacitor in response to receipt of a second VDD control signal; and 3) a power supply capable of receiving the reference voltage on the charge capacitor and generating an output power level, VDD, determined by a level of the reference voltage.

Adaptive voltage scaling power supply for use in a digital processing component and method of operating the same

There is disclosed clock control circuitry for selectively applying a clock signal to a digital processing component wherein the clock signal is capable of being changed to a plurality of operating frequencies. The clock control circuitry is operable to (i) receive a command to change a first operating frequency to a second operating frequency, (ii) in response to the command, disable the applied clock signal, (iii) generate a test clock signal having the second operating frequency, (iv) apply the test clock signal to a power supply adjustment circuit, and (v) sense a status signal from the power supply adjustment circuit. The status signal indicates that a power supply level of the digital processing component has been adjusted to an optimum value suitable for the second operating frequency.

Adaptive voltage scaling clock generator for use in a digital processing component and method of operating the same

A polysilicon resistor is added between a source (ground or power) of an EMI core circuitry and a source of the EMI peripheral circuitry. In this way, the electromagnetic interference of an integrated circuit is reduced. The added polysilicon resistor reduces the di/dt of the current passing between the power and the ground of the EMI core circuitry so that the EMI is reduced.

Layout solution for electromagnetic interference reduction

A MOS precision capacitor is formed in an integrated circuit including a p-mos and n-mos transistor without adding to the process steps used in forming the p-mos and n-mos transistor. The MOS precision capacitor includes a n-well formed concurrently with a n-well of the p-mos transistor, a n-type region formed concurrently with a threshold adjust region of the p-mos transistor, an oxide layer formed concurrently with gate oxide layers of the p-mos and n-mos transistors, a first electrode formed over the n-type region, at least one n+ region formed concurrently with source and drain regions of the n-mos transistor by self aligning to the sidewall of the first electrode, and a second electrode connected to the at least one n+ region. Good gate oxide tracking between the MOS precision capacitor, the p-mos transistor, and the n-mos transistor, is provided by forming the n-type region of the MOS precision capacitor with a dopant concentration approximately equal to that of the threshold adjust region of the p-mos transistor, and approximately within an order of magnitude of that of the n-mos transistor. Good ground isolation for the MOS precision capacitor is provided by forming the MOS precision capacitor in its own n-well. Low voltage and signal frequency dependency for the MOS precision capacitor is provided by respectively forming the n-type and n+ regions between the first and second electrodes of the MOS precision capacitor such that their respective dopant concentrations are greater than that of the n-well.

Growing community of inventors

San Jose, CA, United States of America

Bruno Kranzen