Stmicroelectronics S.a.

Bruno Fel

Andrew Cofler

Laurent Ducousso

St&eacute;phane Bouvier

Program code intended to be copied into the cache memory of a microprocessor is transferred encrypted between the random-access memory and the processor, and the decryption is carried out at the level of the cache memory. A checksum may be inserted into the cache lines in order to allow integrity verification, and this checksum is then replaced with a specific instruction before delivery of an instruction word to the central unit of the microprocessor.

Method for protecting a program code, corresponding system and processor

A computer system supplies instructions simultaneously to a plurality of parallel execution pipelines in either superscalar mode or very long instruction word mode with checks for vertical and horizontal dependency between instructions, the horizontal dependency checks between instructions supplied in the same machine cycle being effective in superscalar mode but disabled in very long instruction word mode.

Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modes

Instructions in a computer system are executed in a plurality of parallel execution pipelines, a horizontal dependency check is carried out between instructions supplied to the parallel pipelines and in response to detecting horizontal dependency a control signal of a first or second type is generated depending on whether the dependency can be resolved by activating a by-pass or whether a temporary stall is required in one of the pipelines.

Computer system that operates in VLIW and superscalar modes and has selectable dependency control

A computer system has a memory which holds a computer program consisting of a sequence of program instructions. The format of the program instructions depends on an instruction mode of the computer system. A decoder is arranged to receive and decode program instructions. A microinstruction generator is responsive to information from the decoder to generate microinstructions according to a predetermined microinstruction format which is independent of the instruction mode of the computer system. The computer system has a plurality of parallel execution units for receiving and executing the microinstructions.

Execution of a computer program

A computer system has a plurality of parallel execution units for executing instructions with assigned guard indicators, one execution unit including a master guard value store and another execution unit having a shadow guard value store, together with guard ownership circuitry to indicate whether the shadow guard value store owns the current value of the guard indicator and transfer circuitry operable to transfer a guard value from the master store to another execution unit.

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Voreppe, France

Bruno Fel