Nec Corporation

3com Corporation

Zenith Data Systems Corporation

Packard Bell Nec

Other

Bull Hn Information Systems, Inc.

Bruno DiPlacido, Jr

Thomas F Joyce

Jian-Kuo Shen

Chester M Nibby, Jr

Jeffrey S Somers

Thomas L Murray, Jr

James F Bertone

Michelle A Pence

G Lewis Steiner

Martin Massucci

Marc Sanfacon

Lance J McNally

William S Wu

Suresh K Marisetty

Puthiya K Nizar

Norman J Rasmussen

Lawrence Aaron Boxer

Richard A Lemay

James W Keeley

Martin M Massucci

Lance T McNally

The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.

Symmetric multiprocessing system with unified environment and distributed system functions

An Ethernet flow control system, preferably for a Ethernet switch, having flow controlled transmitting ports in compliance with IEEE Standard 802.3x. The flow control system includes a shared resource, a plurality of buffers receiving data frames from the shared resource, and a plurality of transmitting ports. Each transmitting port being associated with one of the plurality of buffers and being flow controllable between an enabled state and a blocked state. The transmitting port removing and transmitting data frames from the associated buffer when in the enabled state. Each transmitting port including a timer for measuring the time that an associated buffer has a data frame and the corresponding transmitting port is in the blocked state. Each port also includes control logic for removing data frames from the associated buffer when the measured time is greater than a predetermined time.

Method and device for controlling data flow in a computer data network

A network data switch includes a transmit buffer memory containing transmit buffers allocated to temporarily store data frames being transmitted on attached network links. Multicast frames are replicated into different transmit buffers as necessary for transmission on the corresponding network links. Multiple-cycle write and read phases of the transmit buffer memory are defined, and the transmit buffer memory is operated in different modes for unicast and multicast operation. For a unicast frame, multi-word segments of the frame are written into the correct transmit buffer during successive write phases. Each segment is written during a write phase as a burst of data words at a high data rate. For a multicast frame, words of the frame are written in a time-slice manner into the transmit buffers for the network links on which the frame is to be transmitted. The words are written during successive write phases. During each write phase a single word is written to all the necessary transmit buffers by being supplied to the buffer memory data input while the buffers are sequentially addressed.

Frame replication in a network switch for multi-port frame forwarding

A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.

Symmetric multiprocessing system with unified environment and

A multiported device is provided connected to a switching device providing switching functions. The multiported device receives frames and is connected to an application processor. Some of the received frames are passed to the application processor via an application processor port having a port bandwidth. The multiported device includes an application receive buffer having a receive buffer size for storing frames and providing frames to the application processor for processing. A programmable logic unit is provided for monitoring a level of data in the receive buffer and monitoring a type of frame forwarded to said application processor. The frames each have a discriptor frame associated with it with data indicating one or more of priority status and broadcast/unicast status. The logic unit monitors the level of data based on at least one threshold level for dropping frames upon a data level in said receive buffer reaching the threshold level which have a status. The status is one the one or more of priority status and broadcast/unicast status.

Dynamic threshold packet filtering of application processor frames

Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.

Adaptively generating timing signals for access to various memory

A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.

Bus controller having state machine for translating commands and

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Dedham, MA, United States of America

Bruno DiPlacido, Jr