International Rectifier Corporation

Other

Ternational Rectifier Corporation

Bruno Charles Nadd

Vincent Thiery

Xavier De Frutos

Chik Yam Lee

Thomas J Ribarich

Andre Mourrier

John J Ribarich

Daniel Marvin Kinzer

Mark Pavier

Niraj Ranjan

Talbott Mead Houk

David C Tam

Glyn Connah

Vincent Thierry

Xavier Frutos

A synchronous rectifier comprising a MOSFET device, and a gate driver for driving the gate of the MOSFET device, the MOSFET device comprising first and second MOSFET transistors coupled with their drain-source paths in parallel to receive an alternating current waveform for rectification by the drain-source paths of the MOSFET transistors, the first transistor having a low Rdson and the second transistor having a high Rdson whereby the apparent Rdson of the MOSFET device is increased when the current through the MOSFET device is below a threshold thereby enabling zero crossing detection.

Method and apparatus for driving a power MOS device as a synchronous rectifier

A method of driving a power transistor switch comprising: receiving a drive input signal; converting the drive input signal into a converted drive input signal; and providing the converted gate drive input signal to a control electrode of the switch to turn on the switch, the converted drive input signal having three regions with respect to time, each having a slope, a first region in time having a first slope up to a Miller Plateau of the switch; a second region in time having a second slope with a reduced slope compared with the first slope; and a third region having a third slope that is greater than the second slope, whereby the control electrode voltage rapidly reaches the Miller Plateau voltage, then more slowly reaches a threshold voltage of the switch and then, when the switch has substantially fully turned on, the control electrode voltage is rapidly increased. The switch delay time is also maintained substantially constant by adjusting the transistor control electrode precharge voltage.

Driver circuit and method with reduced DI/DT and having delay compensation

An active clamp circuit for avalanching and clamping voltage at a gate terminal of a first transistor connected to a power source. The active clamp circuit includes a second transistor for turning ON the first transistor; a third transistor having EPI breakdown voltage less than that of the first transistor; a resistor coupled between a node and source and gate terminals of the third transistor; and an amplifier for comparing voltage on the resistor to a reference voltage and providing an output signal to control the second transistor, wherein, when the third transistor avalanches and the voltage across the resistor exceeds the reference voltage, the output signal turns ON the second transistor thereby clamping the gate terminal of the first transistor, wherein the active clamp circuit tracks the channel characteristic of the first transistor.

Active clamp for semiconductor device

A power converter provides constant load power while achieving a high power factor in a single stage configuration with reduced component count and ratings. The power converter takes a rectified line input to a switching half-bridge that supplies current to a load. A series combination of shunt switch and capacitor is connected across the load to store energy from the input and supply energy to the load. The switches are operated with conduction angles that achieve constant power supplied to the load while drawing a sinusoidal current in phase with the input voltage to achieve high power factor. The circuit provides a simplified configuration over prior power converters that may be used with a resonant load as part of an electronic ballast or an AC-to-DC converter. The power converter configuration and operation also achieves a low total harmonic distortion on the input line power.

Single stage PFC and power converter circuit

An IGBT device, comprising a substrate having a conductivity type; a drain electrode arranged on a bottom surface of the substrate; an epitaxial layer arranged on the substrate and having a conductivity type opposite that of the substrate; at least one body diffusion arranged within the epitaxial layer and having a conductivity type the same as that of the substrate; at least one source diffusion arranged within the body diffusion and having a conductivity type the same as that of the epitaxial layer; a gate electrode to control the IGBT device; a source electrode electrically coupled to the body diffusion and the source diffusion; an additional diffusion arranged within the epitaxial layer and having a conductivity type the same as that of the substrate, the additional diffusion forming a collector region of a vertical bipolar arrangement in the IGBT; and a sense electrode electrically coupled to the additional diffusion; wherein the presence of minority carriers in the epitaxial layer may be detected in accordance with a voltage of the sense electrode.

MOSgate driver integrated circuit with adaptive dead time

A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

Method for operating an H-bridge drive utilizing a pair of high and low side MOSFETS

An audio amplifier comprising a Class D audio amplifier having an input receiving an analog input signal, a pulse width modulation stage for converting the analog input signal to a pulse width modulated signal, a driver stage receiving the pulse width modulated signal and for producing a driver PWM signal and an output switching audio amplifier stage receiving the driver PWM signal and providing an amplified PWM signal; an output filter stage receiving the amplified PWM signal for converting the amplified PWM signal into an analog audio signal; and a linear output amplifier stage receiving as inputs the analog input signal and the output of the output filter stage, the output of the output filter stage serving to bias the linear output amplifier stage. In one embodiment, two floating power supplies are superimposed on the output of the filter stage for biasing the linear amplifier, one at a preset voltage above the output signal of the filter stage and a second at a preset voltage below the output of the filter stage. The linear output amplifier stage provides an analog output to a sound reproduction transducer.

Class AD audio amplifier

A circuit for protecting a power switch in the event of a reverse battery connection, wherein the power switch comprises a MOSFET having a body diode and the MOSFET is connected in series with a load, the circuit comprising terminals connected to the circuit and normally connectable to respective positive and negative power potentials of the battery, and the circuit comprising a switching circuit coupled to the terminals such that the switching circuit turns on the power switch in the event that the terminals are connected with a reverse battery connection.

Reverse battery protection circuit for power switch

A cellular MOSgated device of planar or trench topology has base injection regions formed between pairs of cells to inject minority carriers to modulate the resistivity of the drift region.

IGBT with injection regions between MOSFET cells

H-bridge drive utilizing a pair of high and low side MOSFET's in a common insulation housing

Apparatus for indirectly sensing the temperature of a power MOS device comprising a power MOS device having a current sense circuit for sensing the current in the power MOS device, a circuit for producing a voltage related to the drain-source voltage of the power MOS device, a comparator coupled to receive at a first input the voltage related to the drain-source voltage of the power MOS device and at a second input a voltage related to the current in the power MOS device, the comparator generating an overtemperature protection signal when a predetermined inequality between the voltages at the first and second inputs to the comparator occurs.

Method and apparatus to remotely sense the temperature of a power semiconductor

An electronic fuse comprising an integrated circuit having a control output terminal coupled to a control electrode of a power semiconductor switching device, the power semiconductor switching device being coupled in series with a load between first and second potentials, the integrated circuit further comprising a current sense input for sensing the current through the power semiconductor switching device, the integrated circuit further comprising a driver circuit for driving the power semi-conductor switching device, the driver circuit being coupled to a current limiting circuit responsive to the sensed current in the power semiconductor switching device, the current limiting circuit controlling the driver circuit whereby if the current through the power semiconductor switching device exceeds a predetermined threshold, the current limiting circuit generates a command to pulse the power semiconductor switching device on and off in a period of pulsed operation to maintain the current in the power semiconductor switching device below a predetermined level, further comprising a first timer circuit for limiting the period of pulsed operation to a preprogrammed first duration and further for controlling the power semiconductor switching device whereby if two commands to pulse the power semiconductor switching device are generated by the current limiting circuit within a duration less than a predetermined second duration, the power semiconductor switching device is turned off.

Electronic fuse

A bootstrap capacitor charging circuit comprising first and second power switching transistors arranged in a half bridge arrangement such that the first and second transistors are disposed between a high side potential and a low side potential, a driver circuit for driving the first and second transistors, a bootstrap capacitor adapted to be charged from a potential source and for providing a voltage source to power an electronic circuit, a charging circuit providing a charging path from one of the high and low side potentials to the bootstrap capacitor, first and second series connected switches arranged between a common node of the first and second transistors and one of the high and low side potential, the bootstrap capacitor having a first terminal coupled to be charged by the charging circuit and a second terminal coupled to a common node between the first and second series connected switches; and a control circuit operating in first and second modes, wherein in a first mode when the first and second power switching transistors are switching at a rate above a predetermined frequency, a first of the switches connected to the common node of the first and second power switching transistors is controlled on and the second switch is controlled off; and wherein, when the first power switching transistor is on for a duration of time exceeding a preset duration, the control circuit operates in a second mode wherein the first and second switches are alternately turned on and off for first and second predefined periods of time whereby the bootstrap capacitor charges through the second switch and the charging circuit during the second predefined period of time.

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Lourmarin, France

Bruno Charles Nadd