International Business Machines Corporation

Lenovo (Singapore) Pte. Ltd.

Bruce Wile

David R Engebretsen

Jaimeson Saley

Stephen A Knight

William Vincent Huott

Scott Barnett Swaney

Dean G Bair

Edward James Kaminski, Jr

When testing or validating a hardware system, a script file representing a portion of the firmware may be used to test the system instead of using the firmware code itself. For example, the script file may be plurality of register commands that perform the same initialization sequence as the firmware. Before connecting the hardware system to firmware drivers, the script file may be used to debug the initialization sequence. Instead of generating this script file manually, a firmware testing tool may be used. While executing the firmware, the tool may record the different register access commands performed during the initialization process. The script file is then generated programmatically using these recorded commands without requiring input from the system designer. The generated script file may then be tested on the hardware system to determine whether the command sequence in the script file forces the hardware system into the desired state.

Firmware generated register file for use in hardware validation

Techniques are disclosed to reduce crossover between traffic from switch elements of different switch domains in a distributed switch. Addition of a first switch element to the distributed switch is detected. The distributed switch includes multiple switch elements at least subsequent to the addition, and each switch element has a switch element identifier and a fabric identifier. The respective fabric identifiers of the first switch element and of a second switch element are retrieved. The second switch element is communicably connected to the first switch element via a link, and the link is configured to allow only command traffic to be transmitted via the link. Upon a determination that the fabric identifier of the first switch element does not match the fabric identifier of the second switch element, then no command is issued specifying to reconfigure the link to allow at least one additional traffic type, different from command traffic.

Fencing off switch domains

Disclosed is a method for creating a verification environment to drive a Branch History Table. It consists of two components. First, a method for creating instruction streams for controlling the stress on branch history table logic. The second is a method for pre-loading the branch history array to allow for interesting simulations at the beginning of the test.

Method for creating a simulation environment for enhanced logic verification of a branch history table

A method for verifying all intermediate results of a set of architected registers at the end of an instruction stream, even if the final values do not depend on the values of all intermediate results, using a single MISR (Multiple Input Shift Register) to generate a signature of all updates to multiple architected registers. Single instructions update multiple registers across multiple machine cycles, and an accumulation register allows order independence of partial results. A register update consists of the data to be written, an address identifying which register is to be updated, and controls to identify if this is the last register update that will be done by the current instruction. For each cycle, logic evaluates the update controls to select what will be gated into the accumulation register and also sets MISR control latches to tell how to update the MISR the next cycle. The latched MISR controls select whether the MISR will clear, hold, or evaluate. The expected final MISR value (signature) is compared to the actual final MISR value (signature). A mismatch indicates a functional error during execution of the instruction stream.

Multiple input shift register (MISR) signatures used on architected registers to detect interim functional errors on instruction stream test

A. system (i.e. a tool set) provides logic verification at the logic design level in which an external stimulus to the design is derived from a series of generalized timing diagrams that obey the interface protocols of the logic design under test. A timing diagram editor provides a graphical user interface that allows the logic designer to describe his or her logic in a general timing diagram format incorporating permutations of the interface specification. The output of the timing diagram editor is a file that describes the interfaces of the logic; this file can contain multiple timing diagrams that describe different interface interactions. A suitable simulation driver reads the file created by the timing diagram editor, learns the interfaces described therein, and uses simulation randomization algorithms to drive the interfaces with legal scenarios for the interfaces described in the timing diagram.

Growing community of inventors

Poughkeepsie, NY, United States of America

Bruce Wile