Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Bruce Walter McNeill

Shaohua Yang

Weijun Tan

James Arthur Bailey

Peter John Windler

Jason D Byrne

Wei Tjan Lim

A measurement circuit is provided for measuring the resistance of a variable resistance element biased with an external voltage supply. The measurement circuit includes an analog-to-digital converter (ADC) and a reference generator connected with the ADC. The ADC is operative to receive a reference voltage and a first voltage developed across the variable resistance element, and to generate a digital output signal indicative of a relationship between the first voltage and the reference voltage. The reference generator is operative to generate the reference voltage as a function of the external voltage supply.

Analog-to-digital converter with power supply-based reference

A method includes designating a first sampling phase for a signal captured from a magnetic storage medium, where the signal is representative of information stored by the magnetic storage medium. The method further includes capturing a first waveform associated with the signal at the first sampling phase. The method also includes designating a second sampling phase different from the first sampling phase for the signal. The method further includes capturing a second waveform associated with the signal at the second sampling phase. The method also includes interleaving the first waveform and the second waveform to form an oversampled waveform. The first waveform and the second waveform are captured at a rate at least substantially equal to a rate at which the information stored by the magnetic storage medium was written to the magnetic storage medium.

Oversampling storage system captured waveform

Various embodiments of the present invention provide systems and methods for sync mark detection. As an example, a sync mark detection circuit is discussed that includes a storage circuit, a plurality of noise predictive filter circuits, and a controller circuit. The storage circuit is operable to store a data input as a stored input. The plurality of noise predictive filters are operable to receive a processing input. At least one of the noise predictive filters is selectably modifiable to either increase the probability of finding a sync mark in the processing input or to maintain a baseline probability of finding the sync mark in the processing input. The controller circuit is operable to determine an operational mode that may be a standard operational mode, a bit flipping mode, or a filter modification mode.

Systems and methods for retry sync mark detection

Various embodiments of the present invention provide systems and methods for analog to digital conversion. As an example, a circuit for converting analog signals to digital signals is disclosed. The circuit includes a variable gain amplifier circuit, an analog to digital converter circuit, and a summation circuit. The variable gain amplifier circuit is operable to apply a first gain value to an input to yield a first amplified output, and to apply a second gain value to the input to yield a second amplified output. The analog to digital converter circuit is operable to receive a derivative of the first amplified output and to provide a corresponding first digital sample, and to receive a derivative of the second amplified output and to provide a corresponding second digital sample. The summation circuit is operable to combine the first digital sample and the second digital sample.

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Yokohama, Japan

Bruce Walter McNeill