Hewlett-Packard Company

Hewlett-Packard Development Company, L.p.

Bruce W Melvin

Bharat K Singh

Robert Lee Faulk, Jr

Daniel J Dove

Patricia Ann Thaler

Ballard Claude Bare

A method and system for initiating selective flow control within a network multiplexer. Each port of a network multiplexer is associated with high and low threshold values, as well as a list of indications of ports that have requested the port to initiate flow control and a list of indications of ports which the port has requested to initiate flow control. A port that, by queuing a message descriptor to the transmit queue of a destination port, causes the number of message descriptors queued to the transmit queue of a destination port to equal or exceed its high threshold, is flow controlled by the destination port. When the number of message descriptors queued to the transmit queue of a destination port that previously equaled or exceeded the high threshold falls below the low threshold, all ports flow controlled by the destination ports are released from flow control.

Method and system for output flow control in network multiplexers

A method and system for storing and accessing associations between network addresses and ports within a network multiplexer. The method and system implement an address table containing indexed address/port pairs. Multiple hash functions are applied to an input address in order to identify indexes of address table entries in which the input address may be stored. If the entries indexed by application of the multiple hash functions to an input source address are neither empty nor contain the input source address, then contents of one of the entries is discarded, and the input source address is placed into the now empty entry. Over time, discarded addresses are re-entered into the address table in a fashion equivalent to hash table reshuffling, but the computational inefficiencies inherent in hash table reshuffling are deferred and largely avoided.

Method and system for automatic address table reshuffling in network multiplexers

A method and system for preventing the transmission of stale communications packets by a network multiplexer. Common network hardware and protocol specifications require that communications delayed in transit through a network multiplexer must be discarded after a specified period of time. The method and system employ single bit flags within transmit queue entries to flag queue entries that become stale due to the passage of time while communications packets received by a network multiplexer are stored within the network multiplexer for subsequent transmission. A global clock within the network multiplexer invokes a transmit queue monitoring function at one-second intervals. The transmit queue monitoring function discards queue entries having single bit flag values of &ldquo;1,&rdquo; and sets the bit flag values of the remaining queue entries to &ldquo;1&rdquo;. In this manner, queue entries are discarded after residing within the queue for between slightly more than one second and slightly less than two seconds. Known queue entries can reside in the queue for two seconds or longer.

Method and system for enforcing maximum transit delay in network multiplexers

A laptop computer is coupled to a first port of a network hub for the purpose of assigning a logical address to it. The network manager depresses a front panel button on the hub to activate a logical address learn mode. The network manager types a &ldquo;ping&rdquo; command into the laptop, specifying as the logical destination address the address to be adopted by the hub. The laptop, unable to find a matching physical address for the logical address, issues an address-resolution packet (ARP). The hub responds by adopting the destination address as its logical address and exiting learn mode; the hub replies with its physical address. The laptop, now informed of the hub's physical address, issues the ping request. The hub responds normally to this request, providing confirmation at the laptop that the logical address has been properly assigned. The present invention thus provides for hubs and other network infrastructure devices that can be programmed using universally available commands and without dedicated non-network ports.

Network device with logical-address learn mode

The present invention provides an improved shared memory switching method in which a guaranteed minimum number of buffers per output port is reserved for each input port. The shared memory may also be optionally divided into reserved and unreserved buffers, with the guaranteed minimum number of buffers being provided from the reserved buffers. The unreserved buffers are available to any port and will handle burst communications and other events that cause a given input port's allocation of reserved buffers to be exhausted. So that bursts are also handled fairly among input ports, additional optional features of the present invention include limiting the number of unreserved buffers that may be consumed by a single input port. For fairness among output ports, method also preferably fairly allocates unreserved buffers among the output ports.

Nonblocking and fair queuing switching method and shared memory packet switch

Apparatus is disclosed for automatically configuring network media connections of end node interfaces as well as node interfaces that operate as a hub, a switch or a repeater in a Local Area Network. The apparatus utilizes a pseudo-random sequencer to prevent lock step operation whereby the connections cannot be properly configured.

Apparatus for automatically configuring media connectors of a node interface device

A dual channel 100Base-T link for use between devices in a computer network system. The IEEE 802.3 standard for bus network systems calls for a device interconnection cable which includes four twisted pairs of wire. For 10BaseT and 100Base-T systems, the 802.3 standard specifies the use of only two of the four pairs. The present link includes a special Media Access Controller having dual channel interconnections, and primary and secondary Media Independent Interfaces and Physical Layers. This provides first and second communication channels which are parallel, but cooperating. The second channel is connected to the normally unused two pairs in the cable, effectively doubling the bandwidth of the link without running a new cable.

Dual channel 100Base-T link for computer networks

Apparatus for automatically configuring network media connections

A configuration apparatus for network devices. A plurality of LEDS on the front panel of a network device has a primary mode, displaying device and port status. These LEDS are grouped in a matrix, consisting of pairs of LEDS arranged in a plurality of parallel columns. Textual information may be provided adjacent each of the pairs, to describe an associated secondary mode, for configuration of the features and operational states of the device. When a configuration switch and mode control circuitry are enabled, drivers for the LEDS are disconnected from the ports. A configuration cycle is initiated, during which at least some of the LEDS provide visual cues to the user for carrying out the configuration operations. Sequential and unison blinking of the LEDS, as a group, individually, and in pairs, confirms reconfiguration opportunity, selection, and execution, for each secondary function.

Apparatus and method for configuring a computer networking device

A multi-segment repeater includes a first inter-repeater bus and a second inter-repeater bus. A first repeater circuit is connected to the first inter-repeater bus and to the second inter-repeater bus. The first repeater circuit includes a 10 megabit repeater core, and one or more 100 megabit repeater cores. A selector selects which of the repeater cores is to be connected to the first inter-repeater bus. Additionally, provision is made to allow a 100 megabit repeater core to be connected to the second inter-repeater bus.

Flexible multi-frequency repeater

A processor performs data transactions. For a first data transfer between the processor and a first external device which uses non-multiplexed data transactions, a first address is placed on an (external) address bus and first data is transferred on an (external) address/data bus. A second data transaction is performed between the processor and a second external device which uses multiplexed data transactions. In an address phase of the second data transaction, a second address is placed on the address/data bus. In a data phase of the second transaction, second data is transferred on the address/data bus.

Microprocessor with versatile addressing

A combination of a standardized high speed switch interconnect scheme and global management makes a stack of multiple switches appear as one large managed high speed switch without impeding the transmission of information between individual switches within the managed switch, thereby providing a high speed connection between networking devices. Standard two port PCI bridges are interconnected such that an apparent three port bridge is created. This allows a transaction between systems to occur without interrupting intermediate systems. By logically connecting the PCI bus of one system to that of another, a processor in one system is allowed to access all devices in all the systems that are connected in the stack. In this way only one processor or management entity is required to configure and control a group of stacked systems.

Network inter-product stacking mechanism in which stacked products

An improved interface isolation and selection circuit for a local area network. The invention includes a power supply effective to provide an isolated output voltage. An opto-isolator transforms a first control signal to a second control signal effective to activate the interface. The opto-isolator includes an optical emitter for providing an optical signal in response to the first control signal and an optical detector for receiving the optical signal and providing the second control signal in response thereto. The second control signal is effective to activate the interface by applying the isolated power thereto. In particular implementations, the isolated power and the power for the opto-isolator are provided by a single power supply and a field effect transistor is activated by the opto-isolator and, in turn, activates the interface.

Growing community of inventors

Roseville, CA, United States of America

Bruce W Melvin