Motorola Corporation

Bruce R Yeung

David Q Ngo

Shih K Cheng

Han-Bin K Liang

Jun Ma

Edward T Spears

A monolithic integrated circuit die (10) is fabricated to include unilateral FETs (113, 114, 115), RF passive devices such as a double polysilicon capacitor (57), a polysilicon resistor (58), and an inductor (155), and an ESD protection device (160). A first P.sup.+ sinker (28) provides signal isolation between two FETs (113, 115) separated by the first sinker (28) and is coupled to a source region (86) of a power FET (115) via a self-aligned titanium silicide structure (96). A second P.sup.+ sinker (29) is coupled to a bottom plate (44) of the double polysilicon capacitor (57). A third P+ sinker (178) is coupled to a source region (168) of the ESD protection device (160) via another titanium silicide structure (174).

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Chandler, AZ, United States of America

Bruce R Yeung