Massachusetts Institute of Technology

Gte Internetworking Incorporated

Rolm Systems

Logic Devices Incorporated

Bruce R Musicus

Jeffrey I Robinson

William S Song

Keith Rouse

Robert David Preuss

Donald J Hejna, Jr

Andrew S Crowe

In the control system disclosed herein, multiple input data streams are processed or filtered to generate multiple output streams by a filter which combines efficient batch processing of a fixed number of older input samples with immediate direct processing of a varying number of current samples thereby to generate multiple output data streams which are based on essentially current input data as well as older input data reaching back for a time interval which varies periodically.

Digital filter and control system employing same

A programmable integrated signal processor ('SPROC') is provided having a multiported central memory unit (RAM), a program memory, at least one, and preferably a plurality of digital processors coupled to the multiported RAM and to the program memory, a data flow manager which controls external data flowing into the SPROC and processed data flowing out of the SPROC by acting as an interface of such data with the multiported RAM, input and output ports coupled to the DFM and acting as serial interfaces for the SPROC, and a host port permitting the programming of the SPROC and acting as a parallel interface to the SPROC. SPROCs may be coupled via the input and output ports to provide a system. The SPROC architecture permits the SPROC system to be computationally expandable, to have low latency and parasitic overhead for real time I/O, to efficiently execute a multiple of asynchronous processes, and to easily interface with microprocessors of various formats. The SPROC architecture in conjunction with a compiler and user interface system permits a user to 'sketch and realize' complex circuits in the SPROC. An access port coupled to the multiported data RAM and the program RAM is provided for debugging purposes and permits reading and writing to data and program RAM memory locations. A probe permits monitoring of a memory location and provides an analog signal indicative thereof. The SPROC accomplishes for signal processing that which a microprocessor accomplishes for logic processing, and is further also easily realized in silicon.

Real time programmable signal processor architecture

Method for time-scale modification ('TSM') of a signal, for example, a voice signal, wherein starting positions of blocks in an input signal, referred to as analysis windows, are varied and an output signal is reconstructed by overlapping analysis windows using fixed window offsets, i.e., the duration of overlap between analysis windows is fixed during reconstruction. This is done by searching for segments of the input signal which are similar to the previous portion of the output signal. In one embodiment of the present invention a cross-correlation is used as a similarity measure to evaluate such similarity and the cross-correlation uses a fixed, predetermined minimum number of samples. The starting position of the analysis window which results in the greatest similarity in overlapping regions is determined as the starting position which provides the largest value of cross-correlation in the overlapping regions. Several cross-correlations are evaluated by shifting the analysis window over a predetermined number of samples, removing the first shifted samples in the evaluation each time, and using the same, predetermined number of samples in the evaluation to determine the 'best' starting position for an analysis window. Finally, the predetermined number of samples from the beginning of the analysis window are averaged with the predetermined number of samples from the end of the previous portion of the output signal and the remaining samples in the window are appended to the averaged segment of the previous portion of the output signal.

Method for time-scale modification of signals

The machine includes a plurality of processors each performing identical linear processing operations on its input signal. At least one checksum processor is provided to perform the same linear processing operation as the plurality of processors. Computing apparatus using inexact arithmetic forms a linear combination of the input signals to form an input checksum signal and for operating on the input checksum signal with the checksum processor to generate a processed input checksum signal. The same linear combination of the outputs of the plurality of processors is formed to produce an output checksum signal and the output checksum signal is compared with the processed input checksum signal to produce an error syndrome. A generalized likelihood ratio test is formed from the error syndrome for assessing a likeliest failure hypothesis. The fault tolerant multiprocessor architecture exploits computational redundancy to provide a very high level of fault tolerance with a small amount of hardware redundancy. The architecture uses weighted checksum techniques, and is suited for linear, digital, or analog signal processing.

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Arlington, MA, United States of America

Bruce R Musicus