California Institute of Technology

The United States of America As Represented by the Administrator of the

Sandia Corporation

Bruce R Hancock

Bedabrata Pain

Thomas J Cunningham

Guang Yang

Suresh Seshadri

Chao Sun

John K Liu

Frank J Grunthaner

Monico Ortiz

Roger M Smith

Christopher James Wrigley

Kenneth W Newton

David Cole

Michael E Hoenk

Shouleh Nikzad

Todd J Jones

Colin L Smithpeter

Matthew R Dickie

Robert O Nellums

Eddie R Hoover

The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.

Mapping electrical crosstalk in pixelated sensor arrays

A method and circuit for injecting charge into a circuit node, comprising (a) resetting a capacitor's voltage through a first transistor; (b) after the resetting, pre-charging the capacitor through the first transistor; and (c) after the pre-charging, further charging the capacitor through a second transistor, wherein the second transistor is connected between the capacitor and a circuit node, and the further charging draws charge through the second transistor from the circuit node, thereby injecting charge into the circuit node.

Method and circuit for injecting a precise amount of charge onto a circuit node

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Sparsely-bonded CMOS hybrid imager

A latch circuit that uses two interoperating latches. The latch circuit has the beneficial feature that it switches only a single time during a measurement that uses a stair step or ramp function as an input signal in an analog to digital converter. This feature minimizes the amount of power that is consumed in the latch and also minimizes the amount of high frequency noise that is generated by the latch. An application using a plurality of such latch circuits in a parallel decoding ADC for use in an image sensor is given as an example.

Minimal power latch for single-slope ADCs

An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.

Mixed linear/square-root encoded single slope ramp provides a fast, low noise analog to digital converter with very high linearity for focal plane arrays

For a source-follower signal chain, the ohmic drop in the selection switch causes unacceptable voltage offset, non-linearity, and reduced small signal gain. For an op amp signal chain, the required bias current and the output noise rises rapidly with increasing the array format due to a rapid increase in the effective capacitance caused by the Miller effect boosting up the contribution of the bus capacitance. A new switched source-follower signal chain circuit overcomes limitations of existing op-amp based or source follower based circuits used in column multiplexers and data readout. This will improve performance of CMOS imagers, and focal plane read-out integrated circuits for detectors of infrared or ultraviolet light.

Analog bus driver and multiplexer

The present invention provides a CMOS imager with a reset scheme, by which a CMOS imager generates a sub-kTC noise so that read noise does not depend on the sense node capacitance. By using a column feedback circuit, reset noise can be suppressed to a negligible amount so that photogate APS or CCD-like circuits can achieve noise performance to very efficient value. This scheme allows increasing sense node capacitance without increasing the noise and also achieves a large full-well value without sacrificing read noise performance. The feedback circuit in one of the embodiment of the present invention is located at the column side of the circuit. This design provides a minimal change to the pixel. As a result quantum efficiency or pixel size is not compromised. The present invention allows a CMOS imager to capture scene with high intra-scene contracts under low illumination with high dynamic range.

Photodiode CMOS imager with column-feedback soft-reset for imaging under ultra-low illumination and with high dynamic range

An apparatus is disclosed for generating a three-dimensional (3-D) image of a scene illuminated by a pulsed light source (e.g. a laser or light-emitting diode). The apparatus, referred to as a phase-sensitive 3-D imaging camera utilizes a two-dimensional (2-D) array of photodetectors to receive light that is reflected or scattered from the scene and processes an electrical output signal from each photodetector in the 2-D array in parallel using multiple modulators, each having inputs of the photodetector output signal and a reference signal, with the reference signal provided to each modulator having a different phase delay. The output from each modulator is provided to a computational unit which can be used to generate intensity and range information for use in generating a 3-D image of the scene. The 3-D camera is capable of generating a 3-D image using a single pulse of light, or alternately can be used to generate subsequent 3-D images with each additional pulse of light.

Parallel phase-sensitive three-dimensional imaging camera

A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.

Increasing the dynamic range of CMOS photodiode imagers

A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

High-speed on-chip windowed centroiding using photodiode-based CMOS imager

For the growth of strain-layer materials and high quality single and multiple quantum wells, the instantaneous control of growth front stoichiometry is critical. The process of the invention adjusts the offset or phase of MBE control shutters to program the instantaneous arrival or flux rate of In and As.sub.4 reactants to grow InAs. The interrupted growth of first In, then As.sub.4, is also a key feature.

Growth of III-V films by control of MBE growth front stoichiometry

III-V films are grown on large automatically perfect terraces of III-V substrates which have a different lattice constant, with temperature and Group II and V arrival rates chosen to give a Group III element stable surface. The growth is pulsed to inhibit Group III metal accumulation to low temperature, and to permit the film to relax to equilibrium. The method of the invention 1) minimizes starting step density on sample surface; 2) deposits InAs and GaAs using an interrupted growth mode (0.25 to 2 mono-layers at a time); 3) maintains the instantaneous surface stoichiometry during growth (As-stable for GaAs, In-stable for InAs); and 4) uses time-resolved RHEED to achieve aspects (1)-14 (3).

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Altadena, CA, United States of America

Bruce R Hancock