Intel Corporation

Bruce Querbach

Christopher Connor

David G Ellis

Theodore Zale Schoenborn

Pete D Vogt

Kuljit Singh Bains

John B Halbert

David Zimmerman

Jay Joseph Nejedlo

William K Lui

Amjad M Khan

Christopher W Hampson

Ifar Wan

Yulan Zhang

Rajesh Sundaram

Shigeki Tomishima

Srikanth T Srinivasan

Chetan Chauhan

Eric S Gayles

Eshwar Gollapudi

Mohammad A Abdallah

Jawad Basit Khan

David W Grawrock

Rahul Khanna

Christopher P Mozak

Richard L Coulson

James K Pickett

Zion S Kwok

Luke A Johnson

Brian S Morris

Zvika Greenfield

Dong Wang

Tieyu Zheng

Keshavan K Tiruvallur

Woojong Han

Mark B Trobough

Chinna B Prudvi

Hermann Gartler

Vui Yong Liew

Hanmant Pramod Belgal

Bryan L Spry

Mohamed Arafa

Ashok N Kabadi

Sanjib Sarkar

Samie B Samaan

Keith A Drescher

Mukesh Kataria

Sean R Babcock

Mani Prakash

Michael J Tripp

John K Grooms

Lyle E Cool

Ali Muhtaroglu

Russell J Wunderlich

James J Grealish

Philip Abraham

Brian Meyer

Abhijit Davare

Edward L Payton

Christopher E Yunker

Priyadarsan Patra

Philip Hillier

Li Pan

William Penner

Mike J Tripp

Rahima K Mohammed

Ridvan A Sahan

Jeffrey W Ryden

Arun R Ramadorai

Kuan Zhou

Wee Hoo Cheah

Yuen Tat Lee

Kapila B Udawatta

John L Baudrexl

Jayasekhar Tholiyil

Gordon McFadden

Rony Ghattas

Christian E Iovin

Kip C Killpack

Loren James McConnell

Kyle Markley

Ramakrishna Mallela

Charles D Lucas

Randall B Hamilton

Travis K Goff

Minyoung Kim

Amjad M A Khan

Evan J Halprin

Mir M Hossain

Luis Briceno Guerrero

Jiun Long Foo

Marco A Vindas Vargas

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Padmakumar Gopal

Sanjay S Salem

Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

Technologies for performing macro operations in memory

An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.

Memory cell including multi-level sensing

Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

Technologies for providing adaptive memory media management

A method is described. The method includes monitoring reliability, power consumption and performance of a processor and writing reliability, power consumption and performance data of the processor into an embedded non-volatile random access memory that is integrated into the processor's semiconductor chip.

Processor having embedded non-volatile random access memory to support processor monitoring software

A processor semiconductor chip is described. The processor semiconductor chip includes at least one processing core. The processor semiconductor chip also includes a memory controller. The processor semiconductor chip also includes an embedded non flash non-volatile random access memory having a stack of storage cells disposed above the processor semiconductor chip's semiconductor substrate. The embedded non-volatile random access memory is to store boot up program code that, when executed by the processor semiconductor chip, is to analyze a subsequent module of program code so that a maliciously modified version of the subsequent module of program code can be identified. The embedded non-volatile random access memory to also store the subsequent module of program code.

Secure boot processor with embedded NVRAM

Examples include techniques for booting a computing system. A processor semiconductor chip includes one or more processing cores and an embedded non-volatile random-access memory (NVRAM), the NVRAM storing instructions that when executed by the one or more processing cores manages a boot process for a computing system.

Booting a computing system using embedded non-volatile memory

Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements. Other embodiments are described and claimed.

Extended platform with additional memory module slots per CPU socket and configured for increased performance

Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.

Extended platform with additional memory module slots per CPU socket

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.

Selective performance level modes of operation in a non-volatile memory

Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

Supporting multiple memory types in a memory slot

An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low frequency components of the input signal, and an amplifier communicatively coupled to the high pass components and the low pass components to amplify respective signals passed by the high pass components and the low pass components, wherein the low pass components include a level shifter to shift a common mode voltage level of the input signal to a switch threshold voltage for the amplifier in accordance with at least two different types of memory devices. Other embodiments are disclosed and claimed.

Low power and area efficient memory receiver

Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

Integrated circuit reliability assessment apparatus and method

A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.

Memory controller-controlled refresh abort

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Hillsboro, OR, United States of America

Bruce Querbach