Silicon Laboratories Inc.

Cirrus Logic Inc.

Crystal Semiconductor Corporation

Bruce Philip Del Signore

Eric J Swanson

Akhil K Garlapati

Alexander Cherkassky

Donald A Kerth

Aryesh Amar

Douglas F Pastorello

Eric T King

David M Pietruszynski

Jerome E Johnston

Louis J Nervegna

Ron Hulfachor

David R Welland

Axel Thomsen

Navdeep S Sooch

Jerrell P Hein

Qicheng Yu

William Gardei

Lizhong Sun

Frank Den Breejen

David L Medlock

Victor Aguilar

David R Wellard

Jeffrey M Klaas

John O O'Connell

A driver circuit includes two pull-up portions coupled respectively between VDD and first and second driver output nodes and two pull-down sections coupled respectively between ground and third and fourth driver output nodes. The driver circuit is configurable as an RS485 driver or a CAN driver. The active diodes in the pull-up sections are turned off when necessary to prevent unwanted reverse currents between the first and second output nodes and VDD. The active diodes in the pull-down sections are turned off when necessary to prevent unwanted reverse current between ground and the third and fourth output nodes.

High output swing high voltage tolerant bus driver

A method includes selectively coupling first and second input nodes of a capacitive bridge to first and second voltages, respectively, and selectively coupling first and second output nodes of the capacitive bridge to first and second output terminals, respectively, during a first phase of a clock cycle. The method further includes selectively coupling the first and second input nodes to the second and first voltages, respectively, and selectively coupling the first and second output nodes to the second and first output terminals, respectively, during a second phase of the clock cycle.

Circuit including a switched capacitor bridge and method

Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90&#xb0; apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

Synchronous detection circuit and method for determining a bio-impedance of a biological tissue

Synchronous detection circuit and method for extracting magnitude and phase from a waveform

A DC-DC converter includes a plurality of switches configured to be in a first charging mode until current through an inductor reaches a first current threshold to thereby indicate an end of the first charging mode. Responsive to the end of the first charging mode the DC-DC converter is configured to operate in a second charging mode for a time period &#x394;T in which a first side of the inductor is coupled to an input voltage and a second side of the inductor is coupled to a load. Responsive to the end of the time period &#x394;T, the DC-DC converter operates in a discharge mode until current through the inductor reaches its minimum.

Timing based approach for efficient switched mode power conversion

Stacked layers of non-continuous opaque layer structures are disclosed herein that may be configured to block radiation such as visible light or other forms of light, while at the same time allowing penetration of ambient gases. In one example, such non-continuous opaque layer structures may be configured as stacked non-continuous metal layer structures that together fully block penetration of radiation while at the same provide sufficient open spaces between and/or within the metal layer segments of a given integrated circuit layer to meet maximum metal spacing rules. In another example, such non-continuous opaque layer structures may be configured as capacitive structures.

Radiation-blocking structures

An integrator circuit includes a switched capacitor bridge including first and second inputs and first and second outputs. The switched capacitor bridge is configured to sample first and second reference voltages twice per unit time interval. The integrator circuit further includes an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second outputs twice per unit time interval.

Capacitance to digital converter and method

A voltage regulator circuit comprises an error amplifier for generating, an error signal responsive to a reference voltage in a feedback signal. A feedback circuit provides the feedback voltage signal to the error amplifier and a driver circuit provides regulated output voltage responsive to the input voltage in the error signal. Short circuit protection circuitry selectively protects transistors within the error amplifier, the feedback amplifier and the driver circuit responsive to a short circuit protection enablement signal.

5 volt tolerant voltage regulator

An integrated circuit includes USB communication circuitry for communicating via a USB interface. The USB transceiver circuitry transmits data to and from the integrated circuit over the USB interface. The USB transceiver circuitry further provides protection to internal circuitry of the integrated circuit from a 5 volt short circuit on the USB interface.

USB transceiver circuitry including 5 volt tolerance protection

A voltage regulator circuit comprises an error amplifier for generating an error signal responsive to a reference voltage in a feedback signal. A feedback circuit provides the feedback voltage signal to the error amplifier and a driver circuit provides regulated output voltage responsive to the input voltage in the error signal. Short circuit protection circuitry selectively protects transistors within the error amplifier, the feedback amplifier and the driver circuit responsive to a short circuit protection enablement signal.

A voltage reference generator has been discovered that generates a stable reference voltage that is less than the bandgap voltage of silicon for power supply voltages less than 2V, yet provides sufficient voltage headroom to operate a cascaded current mirror. In one embodiment, the voltage reference generator has a power supply rejection ratio of at least 60 dB and has improved noise performance as compared to traditional bandgap circuits. These advantages are achieved by leveraging the low-beta effect of a CMOS bipolar transistor to generate a current proportional to an absolute temperature.

Voltage reference generator circuit using low-beta effect of a CMOS bipolar transistor

A voltage reference generator generates a stable reference voltage that is less than the bandgap voltage of silicon for power supply voltages less than 2V, yet provides sufficient voltage headroom to operate a current mirror. In one embodiment, the voltage reference generator has a power supply rejection ratio of at least 60 dB and has comparable noise performance as compared to traditional bandgap cirucits. These advantages are achieved by subtracting a current proportional to a complement of an absolute temperature from a current proportional to the absolute temperature to generate a voltage having a positive temperature coefficient, which is then added to a voltage that is a complement of the absolute temperature to achieve a voltage that has a low temperature coefficient.

Voltage reference generator circuit subtracting CTAT current from PTAT current

An output buffer circuit drives multiple signal formats. The output buffer circuit reduces duplication of output bond pads on an integrated circuit die. The output buffer circuit reduces a need for including conversion buffers on system boards. A single integrated circuit including the output buffer circuit may meet a variety of applications. The output buffer achieves these results with a programmable output voltage swing and a programmable output common mode voltage. In some embodiments of the present invention, an integrated circuit includes at least one single-ended buffer and at least one differential circuit coupled to a pair of outputs. One of the single-ended buffer and the differential circuit is selectively enabled to provide a signal to the outputs.

Multiple signal format output buffer

A divider is disclosed herein. The divider includes a sequence of divide stages programmably coupled to provide a variety of divide ratios. The divider also includes one or more multiplexers to feedback the output of a divide stage to the input of a divide stage earlier in the sequence of divide stages. The divider may also include duty cycle correction circuitry and self correction logic to correct abnormal logic states. The divide stages can operate in synchronism with each other. Multiplexer functionality, self correction circuitry functionality, and divide stage functionality may be implemented in a combination latch circuit.

Programmable frequency divider

An analog to digital converter system includes first and second delta sigma converters, a calculation engine, and a serial interface on a single chip. The calculation engine is configured to calculate energy, power, rms current and voltage for single phase or wire power meters. Voltage and current are measured with a shunt or transformer, and a divider or transformer, respectively. The serial interface is bidirectional for communication with a microprocessor or controller, and provides a fixed width programmable frequency output proportional to energy. The digital converter system is user system calibratible.

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Hollis, NH, United States of America

Bruce Philip Del Signore