Adaptec, Inc.

Bruce Pember

Honda Yang

Thomas Kennith Geiger

Christine Odero

Brian Thomas Fosco

Disclosed are methods and computer readable media containing program instructions for testing alternating current characteristics of a computer model of an integrated circuit design. The testing implements an associated AVF file and an associated DUT file for the integrated circuit design. The computer readable media includes: (a) program instructions for generating a test file containing data of a parameter of the integrated circuit design, the test file being generated based upon whether a pair of signals are either both inputs, or one is an input and another is an output; (b) program instructions for parsing through a chip file of the integrated circuit design in order to extract netlist information, external signal names, bus definitions, and pull-up information; (c) program instructions for parsing through the DUT file to extract input/output information, channel number information, and timing information; (d) program instructions for splitting data of the AVF file into input vector data and output vector data; (e) program instructions for generating an environment file that assists in simulating a physical test station; and (f) program instructions for running the environment file using the input vector data and the output vector data in order to generate a log that indicates alternating current test results for the parameter data.

Automated alternating current characterization testing

Disclosed is a method for generating AVF test file data for use in testing a simulation of an integrated circuit design, and verifying the generated AVF test file data before they are delivered to a physical silicon version of the integrated circuit design. The generation method includes providing a map file that contains a plurality of identifying statements for each multiple port I/O cell (or also including single port I/O cells) in the integrated circuit design. Then, generate a verilog executable file for the integrated circuit design. The verilog executable file is configured to contain data associated with the map file, a netlist of the integrated circuit design, output enable data derived from the netlist, and AVF data conversion information. The method further comprises executing the verilog executable file along with a test bench that includes the netlist of the integrated circuit design, a set of test files, and models. The execution is configured to produce the AVF test file data and a DUT timing file data. The generated data is then processed through a verification loop that is configured to identify in a log all of the possible errors with the generated test data. The input data used to generate the AVF test file data may then be modified to enable the re-generation of new AVF test file data and new DUT timing file data. If errors are still present, the loop may again be re-run, if the errors are of the kind that would necessitate correction. Once the verification loop has been run to the satisfaction of the test engineer, the test vector data can be applied to the physical test station for use on the physical silicon chip.

Automated test vector generation and verification

A method of configuring scan mode circuitry of an integrated circuit (IC) device includes parsing through an initial file of the scan-flops that are to be included in the scan mode circuitry. The initial file can be prepared with a synthesis tool such as Synopsys. A particular subset of scan-flops are parsed, according to an identified number to be included in each scan chain. A holding tank is created to hold each subset of scan-flops for each scan chain. Each holding tank is then used to form a scan path and to stitch the corresponding scan chain. The parsing of the scan-flops into holding tanks can be performed with a c-shell script. Also, the c-shell script can be called by a Synopsys dc_shell script.

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Redwood City, CA, United States of America

Bruce Pember