Freescale Semiconductor,inc.

Sand 9, Inc.

Analog Devices,inc.

Nxp Usa, Inc.

Bruce Michael Newman

Klaus Juergen Schoepf

Reimund Rebel

Dean A Badillo

Mohammad Asmani

Douglas Alan Garrity

Brandt Braswell

Merit Y Hong

Mohammad Nizam Kabir

Mariam Hoseini

Darren V Weninger

Rex Kenton Hales

An analog-to-digital converter (ADC) and a method are disclosed. The ADC has a quantizer. The quantizer comprises a linear-feedback shift register (LFSR), a decoder configured to provide a plurality of switch control signals at a plurality of decoder outputs, respectively, the plurality of switch control signals responsive to a LFSR value of the LFSR output; an electrical reference, the electrical reference having a plurality of reference outputs, the electrical reference configured to provide a plurality of reference levels at the plurality of reference outputs, respectively; a first switch providing a first switch output and a second switch output; and a comparator, the comparator having a signal input, a first reference input, and a second reference input, the first reference input connected to the first switch output, and the second reference input connected to the second switch output.

Mismatch compensation in an analog-to-digital converter using reference path reconfiguration

Apparatus and methods are described for monitoring temperature of a mechanical resonator. Two or more temperature sensors may be positioned at respective locations to detect a temperature difference between the locations. The temperatures measured by the two or more temperature sensors may be used to determine a temperature of the mechanical resonator.

Frequency correction of oscillators and related apparatus and methods

The embodiments described herein provide a digital-to-analog converter (DAC). The DAC implements a stepped return-to-zero (RZ) pulse scheme, where the DAC output includes the superposition of multiple time-offset RZ pulses. In one embodiment, the DAC includes a first switching element, a second switching element, a current source, and a current sink. The first switching element generates first RZ pulses, and the second switching element generates second RZ pulses, where the second RZ pulses are time-offset from the first RZ pulses. The first RZ pulses and second RZ pulses are combined to provide stepped RZ pulse output signal.

Return-to-zero digital-to-analog converter with overlapping time delayed pulse generation

The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.

Power on reset circuit and method of use

Power-on reset circuit and method

Embodiments include DACs and methods for digital-to-analog conversion. A DAC includes an encoder and a plurality of DAC elements. The encoder maps each of a plurality of bits of a digital input value to one of the DAC elements, and produces a sign indication indicating whether a magnitude of the digital input value is above or below a threshold. Each DAC element produces a DAC element analog output signal that indicates whether a received sign indication and a received bit corresponds to a first state, a second state or a third state (e.g., a zero, positive or negative state). In an embodiment, the DAC uses positive historic mapping information when the magnitude of the digital input value is above the threshold, and negative historic mapping information when the magnitude of the digital input value is below the threshold. DAC elements may be configurable into a Return-to-Zero or a Non-Return-to-Zero mode.

Multiple-bit, digital-to-analog converters and conversion methods

A circuit includes a clock conditioning circuit which receives an encoded clock signal, and provides first and second conditioned clock signals in response. The clock conditioning circuit adjusts a period of the first and second conditioned clock signals in response to an adjustment of a period of the encoded clock signal. The circuit includes a modulator which receives the first and second conditioned clock signals.

Clock conditioning circuit

An analog-to-digital converter (ADC) includes a multiplying digital-to-analog converter (MDAC) having a plurality of capacitors and a plurality of capacitor positions. The ADC generates a random number for a conversion cycle. The ADC configures each capacitor of the plurality of capacitors in a corresponding capacitor position of the plurality of capacitor positions based on the random number for the conversion cycle. The ADC converts, for the conversion cycle, a voltage of an analog signal to a digital value based on the capacitor configurations.

Growing community of inventors

Gilbert, AZ, United States of America

Bruce Michael Newman