International Business Machines Corporation

Sequent Computer Systems, Inc.

Bruce Michael Gilbert

Thomas D Lovett

Donald R DeSota

Robert Joersz

Wayne Alan Downer

Thomas Benjamin Berg

Robert J Safranek

Maged M Michael

Eric N Lais

Mehul M Shah

Robert T Joersz

Michael Grassi

Stacey G Lloyd

Kenneth Frank Dove

Roger Lee Shelton

William Durr

Partitioning a node of a multi-node system into more than one partition is disclosed. First resources of the node are physically partitioned into more than one partition. The first resources physically partitioned to each partition are directly inaccessible by other partitions of the node. Second resources of the node are then internally logically partitioned into the more than one partition. Each second resource internally separates transactions of one partition from transactions of other partitions. Furthermore, the node can be dynamically repartitioned into other partitions, such as a single partition, without having to take the multi-node system down. Operating system (OS) instances of the partitions may have assumptions provided to allow for dynamic partitioning, such as quiescing the processors and/or the input/output components being reconfigured, purging remote cache entries across the entire OS, etc. Each partition may have associated therewith registers that are protected from access by other partitions.

Partitioning of node into more than one partition

A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each entry corresponds to no more than one of the memory modules. The tables support asymmetric population of the memory modules within the ports; each port is capable of having a different number of memory modules relative to the other ports. The tables impose no restrictions on where the memory modules are to be inserted within the ports, both number-wise and position-wise. The tables are independently configurable; the configuration of each table is modifiable independently of the configurations of the other tables. Each table is dynamically configurable. The entries of a table are modifiable to reflect changes in the number and type of the memory modules connected, without restarting or temporarily halting the computer system containing the memory controller.

Memory controller having tables mapping memory addresses to memory modules

Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.

Non-inline transaction error correction

A multiple-stage pipeline for transaction conversion is disclosed. A method is disclosed that converts a transaction into a set of concurrently performable actions. In a first pipeline stage, the transaction is decoded into an internal protocol evaluation (PE) command, such as by utilizing a look-up table (LUT). In a second pipeline stage, an entry within a PE random access memory (RAM) is selected, based on the internal PE command. This may be accomplished by converting the internal PE command into a PE RAM base address and an associated qualifier thereof. In a third pipeline stage, the entry within the PE RAM is converted to the set of concurrently performable actions, such as based on the PE RAM base address and its associate qualifier.

Multiple-stage pipeline for transaction conversion

A method is provided for allocating system resources across multiple nodes of a system communicating through a hardware device. The method provides for allocation of transaction units or identifiers in an allocating component for use in a multiple target component which may be in a distinct target node within the multiple node system. Based on the operations or requests that a target node receives from multiple external request source nodes, each requiring the use of target transaction unit objects such as transaction identification bits, the method provides inclusion of such information in the initial request to a target node which allows any data transmission between the source node and the target node, or the target node and the source node to be accomplished without any further intervention by the allocating component. Such component may be a local memory control agent or device.

Distributed allocation of system hardware resources for multiprocessor systems

A masterless approach binds multiprocessor building blocks to partitions of a computer system using identifiers and indicators. A number of building blocks communicate among each other to determine a partition to which each building block is to be partitioned. For each unique partition to which one or more of the building blocks is to be partitioned, the building blocks communicate among each other to determine building block uniqueness, and then each of the building blocks joins the partition. The building blocks share with one another their logical port identifiers, which uniquely identify the building block within a partition. A commit indicator of each building block indicates that the building block has committed itself to the partition and that its identifiers cannot be changed. A partition protect indicator is set by one building block of a partition, preventing changes to the commit indicators of other building blocks wishing to join the partition except by that one building block, effectively protecting the partition. Building block protect indicators protect the building blocks themselves.

Masterless building block binding to partitions using identifiers and indicators

The assignment of an address to a transaction for serialization purposes is disclosed. A simulated address is assigned to a transaction of a first type. The simulated address may be determined by selecting a mask based on one or more bits of a command type attribute of the transaction, and performing a logical OR operation on the highest bits of the mask with a number of bits determined by concatenating various bits of various attributes of the transaction. The lowest bits of the resulting simulated address can be incremented for each transaction assigned a simulated address having the same highest bits. The transaction is serialized relative to other transactions of the first type, such as I/O-related transactions, utilizing a serialization approach for transactions of a second type. The serialization approach may be an existing approach already used to serialize transactions of the second type, such as coherent transactions.

Address assignment to transaction for serialization

A hazard queue for a pipeline, such as a multiple-stage pipeline for transaction conversion, is disclosed. A transaction in the pipeline is determined to represent a hazard relative to another transaction, such as by evaluating the transaction against a hazard content-addressable memory (CAM). The hazard CAM can enforce various hazard rules, such as considering a transaction as active if it is referencing a memory line and is currently being processed within the pipeline, and ensuring that only one active transaction with a given coherent memory line is in the pipeline at a single time. In response to determining that a transaction is a hazard, the transaction is routed to a hazard queue, such as at the end of the pipeline. Once the hazard is released, the transaction re-enters the pipeline.

Hazard queue for transaction pipeline

The retrieval of all tag entries of cache locations for a memory address is disclosed, as well as the determining of an error correcting code (ECC) for the tag entries based thereon. Tag entries of tag memory that correspond to possible cache locations within an n-way associative cache are retrieved for a memory address. An ECC for the tag entries, based on the entries, is determined, and is stored as part of the entries within the tag memory. The n-way associative cache may be a two-way associative cache, such that there are two tag entries corresponding to two possible cache locations within the cache for the memory address. The ECC for the two tag entries are thus based on the two tag entries.

Retrieval of all tag entries of cache locations for memory address and determining ECC based on same

A method and apparatus for providing cache coherence in a multiprocessor system which is configured into two or more nodes with memory local to each node and a tag and address crossbar system and a data crossbar system which interconnects all nodes. The disclosure is applicable to multiprocessor computer systems which utilize system memory distributed over more than one node and snooping of data states in each node which utilizes memory local to that node. Global snooping is used to provide a single point of serialization of data tags. A central crossbar controller examines cache state tags of a given address line for all nodes simultaneously and issues an appropriate reply back to a node requesting data while generating other data requests to any other node in the system for the purpose of maintaining cache coherence and supplying the requested data. The system utilizes memory local to each node by dividing such memory into local and remote categories which are mutually exclusive for any given cache line. The disclosure provides support for a third level remote cache for each node.

Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent system

Removing building blocks from partitions to which they have been bound is disclosed. A building block of a platform is removed from a partition of the platform by first halting activity by the partition on the building block. A first partition identifier of the building block indicates the partition of the building block. The building block joined the partition in a masterless manner. The resources of the building block are withdrawn from the partition, and the building block is deauthorized from the platform.

Building block removal from partitions

A system and method of partitioning a multiprocessor or multinode computer system containing two or more partitions each of which contain at least three nodes or processors and a central hardware device communicating with a requestor node or processor, a target node or processor and at least one additional node or processor in the partition. The multiprocessor system architecture allows for partitioning resources to define separate subsystems capable of running different operating systems simultaneously. The method operates with the central device, a tag and address crossbar system, which transmits requests for data from the requestor node to the target node, but not to any of the additional nodes or processors which are not defined as part of a given partition. The method provides steps of assignment of definitions to physical ports with the central device corresponding with desired partitioning of resources within the system. Data processed within the system is assigned tags which themselves are related to the defined system resources allocated to one or more desired partitions within the system.

Hardware support for partitioning a multiprocessor system to allow distinct operating systems

A masterless approach for binding building blocks to partitions is disclosed. Other blocks are first sent a first physical port identifier indicating a block's physical location, and a first partition identifier indicating the block's partition. Second physical port identifiers and second partition identifiers are received from the other blocks. The first physical port identifier and the second physical port identifiers of a subset of the other blocks are then sent to the subset, the second partition identifiers of the subset being equal to the first partition identifier. The first physical port identifier and the second physical port identifiers of the subset are also received from each block of the subset. A first logical port identifier indicating the block's logical location is sent to the subset, and second logical port identifiers are received from the subset. The block joins the partition indicated by the first partition identifier.

Masterless building block binding to partitions

An associative cache and method for replacing data entries in the associative cache by marking input-output (IO) device entries with an IO state. The IO state of a data entry may be indicated by a status or state tag. When valid data entries in a cache must be replaced to make way for new data, entries marked with an IO state are replaced first. This order of replacement improves the cache hit rate by non-IO agents such as data processors by preserving their data entries in the cache. If no valid data entries in the associative cache are marked with an IO state, the method reverts to conventional replacement algorithms such as random or least-recently-used (LRU) to determine which data will be replaced.

Growing community of inventors

Beaverton, OR, United States of America

Bruce Michael Gilbert