Integrated Device Technology, Inc.

Bruce Lorenz Chin

Robert H Bishop

David Stuart Gibson

Robert J Proebsting

Prashant Shamarao

Angus David Starr MacAdam

Roland T Knaack

Curt Karnstedt

Mario Montana

Frank D Matthews

A timing controller includes a pipelined delay chain configured to process commands and control signals associated with the commands between a first device and a plurality of second devices having different timing requirements. The pipelined delay chain includes a cascaded arrangement of a primary delay chain, at least one secondary delay chain and a plurality of control signal sequence generators responsive to signals generated by the at least one secondary delay chain. The primary delay chain may include a plurality of serially-linked registers configured to support a pipelining of the commands and a stack configured to support operations to push and pop the control signals associated with the commands to and from the stack.

Timing controllers having partitioned pipelined delay chains therein

A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of inputs electrically coupled to outputs of a corresponding plurality of delay elements in the data pipeline. The latency selection circuit is configured to pass a data pipeline signal from an output of a selected one of the plurality of delay elements in response to a latency control signal. A synchronization circuit is provided, which is electrically coupled to an output of the latency selection circuit. This synchronization circuit, which includes first and second unequal timing paths therein, is responsive to a clock that synchronizes capture of the data pipeline signal selected by the latency selection circuit and a destination code that selects one of the first and second unequal timing paths to be traversed by the captured data pipeline signal as active.

Multiple time domain synchronizer circuits

A communication system includes a packet switch that routes data packets between endpoint devices in the communication system through virtual channels. The packet switch includes output ports each having a link bandwidth for outputting data packets. Each virtual channel is associated with an output port and is allocated a portion of the link bandwidth of the output port. The packet switch receives a data packet identifying a virtual channel at an input port, selects another virtual channel associated with the input port, routes the data packet through the packet switch, and outputs the data packet from the packet switch by using the selected virtual channel. Additionally, the packet switch may select a reliable transmission protocol, a continuous transmission protocol, or a pseudo-continuous transmission protocol for outputting the data packet from the packet switch. In some embodiments, the packet switch modifies the data packet to indicate the selected virtual channel.

Packet switch with configurable virtual channels

Integrated circuit FIFO memory devices may be controlled using a register file, an indexer and a controller. The FIFO memory device includes a FIFO memory that is divisible into up to a predetermined number of independent FIFO queues. The register file includes the predetermined number of words. A respective word is configured to store one or more parameters for a respective one of the FIFO queues. The indexer is configured to index into the register file, to access a respective word that corresponds to a respective FIFO queue that is accessed. The controller is responsive to the respective word that is accessed, and is configured to control access to the respective FIFO queue based upon at least one of the one or more parameters that is stored in the respective word. Thus, as the number of FIFO queues expands, the number of words in the register file may need to expand, but the controller and/or indexer need not change substantially. The register file may include multiple register subfiles, and the controller may include multiple controller subblocks.

Integrated circuit FIFO memory devices that are divisible into independent FIFO queues, and systems and methods for controlling same

Methods of controlling memory buffers having tri-port cache arrays therein include the steps of reading data from a current read register in the cache memory array to an external peripheral device, and writing data from an external peripheral device to a current write register in the cache memory array. Tri-port controller logic and steering circuitry are also preferably provided for performing efficient read and write arbitration operations to make next-to-read and next-to-write registers always available in the cache memory array. The use of four separate registers in the cache memory array, efficient steering circuitry and the tri-port controller logic essentially eliminates the possibility that gaps or stoppages will occur in the flow of data into and out of the buffer memory device during read and write operations. To always maintain a source of available data for reading or available space for writing, even under worst case operating conditions including burst mode operation, the step of performing write arbitration comprises determining a next-to-write register as a first free register in the cache memory array if the current read and write registers are different registers and the step of performing read arbitration comprises determining a next-to-read register as the current write register if the current write register contains next-to-read data relative to data in the current read register. The step of performing read arbitration may also comprise determining the next-to-read register as a second free register in the cache memory array if the current read and write registers are different registers and the next-to-read register is not the current write register, or as the next-to-write register if the current read and write registers are the same register.

Methods of controlling memory buffers having tri-port cache arrays therein

Methods of testing integrated circuits to include data traversal path identification information include the steps of transferring test data into an integrated circuit containing devices therein and then controlling operation of the integrated circuit so that the test data traverses a first path through the devices. At least a portion of the test data and an identification of at least a first portion of the first path are then retrieved from the integrated circuit. This retrieving step may be preceded by the step of overwriting a first portion of the test data with an identification of a first portion of the first path. In the case of a buffer memory device, an identification (e.g., address) of a current write register (receiving test data) may be &ldquo;tagged&rdquo; to a series of test words written into the current write register during test mode operation. Similarly, when the test data is ultimately read from the buffer memory device, an identification of a current read register may be &ldquo;tagged&rdquo; to the series of test words being read from the current read register. The tagged identification may be interleaved into the stream of test data being read from the current read register, may be overwritten into the stream or the address may be separately stored in the device and then provided (along with other path identification and status information) as a serial or parallel stream of identification data from a dedicated test I/O pad.

Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams

Described is a last stage decoder that generates a local word line signal within a bank of a single-ported memory cell array structure. The decoder inputs predecoded global row address signals, as well as predecoded local row address signals. In order to generate the local word line signal, and thus access a memory cell within a given bank, both one predecoded global row address signal, as well as one predecoded local row address signal must be present. The predecoded local row address signal turns on a pass gate transistor, and allows the predecoded global row address signal to pass through the pass gate transistor and create the local word line signal.

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Decatur, GA, United States of America

Bruce Lorenz Chin