Microsoft Technology Licensing, LLC

International Business Machines Corporation

Bruce Lee Worthington

Qi Zhang

Vishal Sharda

Dustin Lyle Green

Yau Ning Chin

Swaroop Kavalanekar

Robert P Fitzgerald

Stephen Berard

Sean McGrane

Brian P Railing

Colette Mary Donnelly

Ranveer Chandra

Anirudh Badam

Stuart Sechrest

Jeffrey Che Fuller

Jason Carl Hendrickson

Thomas J Ootjers

Jing Li

Changjiu Xian

Mehmet Iyigun

Yevgeniy Bak

Shuvabrata Ganguly

Pankaj Garg

Vinod Murli Mamtani

Iulian Doroftei Calinov

Tristan Anthony Brown

Michael John Martino

René A Vega

Wai Yee Peter Wong

Manas Mandal

Goran Marinkovic

Wai Yee Wong

Stephen R Berard

Sean N Mcgrane

A system has one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state. The system also includes one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state. At least one interrupt is allocated to one of the primary power regions, based on interrupt characteristics.

Reducing power by vacating subsets of CPUs and memory

Embodiments are directed to capturing and storing historical data regarding thermal remediations, to predicting and acting on remediation futures and to communicating with applications regarding thermal remediations implemented on the computer system. In one scenario, a computer system determines which thermal remediations are currently being implemented on a monitored computing device. The thermal remediations are based on the monitored computing device's current operating environment including the physical thermal environment and/or the current software execution environment. The computer system further tracks thermal remediation levels for those thermal remediations that are currently being implemented on the monitored computing device, the thermal remediation levels indicating the degree to which each thermal remediation is implemented. The computer system also filters the tracked thermal remediation levels for tracked thermal remediation information that includes information regarding the computing device's current operating environment, and stores the filtered thermal remediation levels in a data store.

Implementing thermal remediations in reaction to execution of software

A method and an apparatus for characterizing performance of a device based on user-perceivable latency. To characterize device performance, a value of a metric may be computed from latencies of operations performed by the device. In computing a value of a metric, latencies may be treated differently, such that some latencies perceivable by a user of the device may have a greater impact on the value of the metric than other latencies that either are not perceivable or are perceived by the user to a lesser degree. Such a performance metric based on user-perceivable latency facilitates identification of computing device that provide a desirable user experience.

Characterizing device performance based on user-perceivable latency

One or more systems and/or techniques are provided for managing a partially encrypted file system, for storage hardware virtualization, and/or for storage management. In example, data may be stored in a partially encrypted file system, where sensitive data is encrypted for security and non-sensitive data is unencrypted, which may mitigate energy usage otherwise used for encrypting non-sensitive data, thus improving battery life. In an example, a storage device may be exposed to applications as a plurality of isolated storage structures where an application is provided data access to an isolated storage structure assigned to the application but not to isolated storage structures assigned to other applications, which may provide hardware level isolation with improved energy efficiency. In an example, a storage management component, configured to provide isolation and encryption, may be integrated into a computing device as an application specific integrated circuit (ASIC) or a system on a chip (SoC).

Power efficient storage management

Automatically changing the brightness of a display device. A method includes, while the display device is at a first brightness power output level, detecting a power saving event indicating that it is desirable to reduce overall power consumed by the display device. The method further includes continuing to operate the display device at the first power output level while attempting to identify a brightness power output level change triggering event. The brightness power output level change triggering event is an event that occurs that makes a change to the brightness power output level of the display device less perceptible to a user. The method further includes detecting a brightness power output level change triggering event. In response to detecting the brightness power output level change triggering event, the method includes changing the power output level of the display device to a second brightness power output level.

Opportunistically changing display brightness

Memory objects may be allocated and re-allocated within a computer system to consolidate infrequently used memory objects to memory regions that may be operated at lower power. During initial allocation of memory objects, the objects may be placed into high power regions. During subsequent periodic analysis, memory objects in high power regions that are infrequently used may be relocated to lower power regions while memory objects in low power regions that are frequently used may be moved to the high power regions. Various heuristics or logic may be used to handle unmovable objects, shared objects, and other types of objects.

Dynamic memory allocation and relocation to create low power regions

A system has one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state. The system also includes one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state. At least one interrupt is allocated to one of the primary power regions, based on interrupt characteristics. At least one thread is allocated to one of the primary power regions, based on thread characteristics. At least one page is allocated to one of the primary power regions, based on page characteristics.

A computing system having a plurality of processing units configured to perform work by having threads assigned to the processing units. A thread scheduler is coupled to the plurality of processors and configured to schedule threads to the processing units. A power manager is coupled to the thread scheduler and controls performance states or idle states of the processing units. The thread scheduler maintains information about current performance state or idle state per processing unit. The information includes a multi-level description of the processing units in the computing system. The multi-level description includes three or more different entry values of different levels for performance state or idle state for processing units. The power manager provides the multi-level description of the processing units to the thread scheduler, which is configured to schedule threads to the processing units based on the multi-level description.

Thread scheduling based on performance state and idle state of processing units

A memory scanning system may scan memory objects to determine usage frequency by scanning each memory object using a mapping of the processes stored in memory. The scanning may be performed multiple times to generate a usage history for each page or unit of memory. In some cases, scanning may be performed at different frequencies to determine multiple classifications of usage. The mapping may create a detailed topology of memory usage, including multiple classifications of access frequency, as well as several other classifications. Based on the topology, the objects in memory may be copied to another storage medium or optimized for performance or power consumption.

Memory usage scanning

A method and a memory manager for managing data storage in a plurality of types of memories. The types of memories may comprise a primary memory, such as DRAM, and a secondary memory, such as a phase change memory (PCM) or Flash memory, which may have a limited lifetime. The memory manager may be part of an operating system and may manage the memories as part of a unified address space. Characteristics of data to be stored in the memories may be used to select between the primary and secondary memories to store the data and move data between the memories. When the data is to be stored in the secondary memory, health information on the secondary memory and characteristics of the data to be stored may be used to select a location within the secondary memory to store the data.

Managing memory with limited write cycles in heterogeneous memory systems

A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.

Non-blocking data transfer via memory cache manipulation

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Bruce Lee Worthington