Motorola Corporation

Freescale Semiconductor,inc.

Spansion Llc.

Other

Nxp Usa, Inc.

Tagmatech, LLC

Bruce L Morton

Ko-Min Chang

Michael Vanbuskirk

Michael Alan Sadd

Clinton C Kuo

Kuo-Tung Chang

Bruce E Engles

George L Espinor

Perry H Pelley

Jon Scott Choy

Patrice M Parris

Keith E Witek

James M Sibigtroth

Kent J Cooper

Michel Bron

Alexis Marquot

Walter J Ciosek

Mark S Aurora

Graham Stout

Anirban Roy

Craig T Swift

Alexander Hoefler

Frank Kelsey Baker, Jr

Jane A Yater

Jerry D Moench

Robert T Smith

Erwin J Prinz

David W Chrudimsky

John A Langan

Michael C Wood

Craig A Cavins

Chad S Gallun

Jeffrey Y Su

Robert Eugene Smith

Henry Y Choe

Eric Boulian

Michael H Chaddock

Yangming Su

Gary T Anderson

A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell. The selectable current path includes a first transistor. A first amplifier is coupled in a first feedback arrangement between the first memory cell and the first transistor. During a read operation of the first memory cell, a current through the first memory cell is substantially equal to a current through the second memory cell. The memory cell may include a magnetic tunnel junction (MTJ).

Sense path circuitry suitable for magnetic tunnel junction memories

A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.

Memory device and method thereof

A memory device includes a first memory cell having a first transistor, a second transistor, and a resistive storage element. During a read operation, sense current is conducted through the second transistor and the first transistor is used to sense feedback voltage at a first terminal of the resistive storage element. During a write operation, current is conducted through the first and second transistors.

Magnetic random access memory (MRAM) and method of operation

Determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

Determining a logic state based on currents received by a sense amplifer

During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

Sense amplifier with capacitance-coupled differential sense amplifier

Memory device and method

Non-volatile memory string module with buffer and method

A data processing system () has an embedded non-volatile memory () that is programmed and erased by use of a high voltage provided by a charge pump (). In order to prevent the non-volatile memory () from being inadvertently programmed or erased during low power supply voltage conditions, the charge pump () is disabled and discharged when the power supply voltage drops below a predetermined value. This is accomplished by enabling a low voltage detect circuit () in response to a program or erase operation being initiated. A control register () will provide a high voltage enable signal to the charge pump () only when a power supply valid signal is received. In another embodiment, the low voltage detect circuit () may be enabled by another condition to protect the data processing system () from an authorized access.

Method and apparatus for protecting an integrated circuit from erroneous operation

A single memory array () has an isolation circuit for isolating segments of a same bit line (SegBL, SegBL) from each other. The isolation circuit () permits memory cells located in one segment () of an array to be read while memory cells of another segment () of the array are being erased. In one example, the isolation circuit () electrically couples the segments during a read or program of memory cells located on the second segment (SegBL). Program information stored in the single memory array may always be accessed while a portion of the same array is erased. Dynamic variation of the size of the isolated bit line segment occurs when multiple isolation circuits are used to create more than two array segments.

Memory bit line segment isolation

A memory array of one-transistor (1T) SONOS bit cells in a common-source architecture is used in conjunction with a reverse read technique to reduce the effect of read disturb. Bit line voltage in the array, during read operation, is constrained to a Vt or less, relative to the control gate, so that read disturb is limited. When information is programmed into a bit cell in the array, the bit line is used as a drain, which has the effect of concentrating charge toward the bitline end of the SONOS transistor. When information is read from a bit cell in the array, the bit line of the selected bit cell is used as a source, instead of a drain. That reversal gives a larger Vt contrast between a 0 and a 1 than a forward read, for a given amount of stored charge. Using the bit line in this manner limits the electric field to which the oxide of the bit cell is exposed, thereby lessening the amount of read disturb, while also improving the magnitude of the read mode signal and, therefore, improving overall tolerance of the read disturb effect.

Non-volatile memory architecture and method thereof

A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.

Program and erase in a thin film storage non-volatile memory

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Austin, TX, United States of America

Bruce L Morton