Intel Corporation

Other

Bruce L Fleming

Tsung-Yuan Charles Tai

Ren Wang

Jr-Shian Tsai

Arvind Mandhani

Mesut A Ergin

Ashish V Choubal

Prakash N Iyer

Belliappa Manavattira Kuttanna

Rajeev D Muralidhar

Harinarayanan Seshadri

Shreekant S Thakkar

Uttam K Sengupta

Achmed Rumi Zahir

Kenneth D Shoemaker

Sanjoy K Mondal

Vishwesh M Rudramuni

Mark Eidson

Rajasekaran Andiappan

Prashanth Kalluraya

Satish B Acharya

Joydeep Ray

Blaise B Fanning

Alexander W Min

Rajesh Bhikhubhai Patel

Sridhar Lakshmanamurthy

Lance E Hacking

Andrew D Henroid

Ajaya V Durg

Kenneth Foust

Uma M Gadamsetty

Ramana V Rachakonda

Anil K Sabbavarapu

Suketu R Partiwala

Shane D Wall

Lee P Noehring

Sami Yehia

Sundar Iyer

In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the controller comprising logic, at least partially including hardware logic, configured to generate a signal to configure the at least one sensor in a notify power state mode and place the signal on a communication bus coupled to the at least one sensor. Other examples may be described.

Sensor bus interface for electronic devices

Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination.

Dynamically entering low power states during active workloads

An apparatus with an ultra low power architecture is described herein. The apparatus includes a first power supply rail, wherein a plurality of subsystems are to be powered by the first power supply rail. The apparatus also includes a second power supply rail, wherein a plurality of autonomous subsystems are to be powered by the power supply rail, wherein the second power supply rail is to be always on, always available, and low power.

Ultra low power architecture to support always on path to memory

Embodiments of a method and apparatus are described for operating a mobile computing device in different modes using different operating systems. An apparatus may comprise, for example, a memory operative to store multiple operating systems, a processor operative to execute the multiple operating systems, an operating system management module operative to select a first operating system when the mobile computing device is in a first mode or a second operating system when the mobile computing device is in a second mode and the mobile computing device is coupled to one or more external devices. Other embodiments are described and claimed.

Method and apparatus for multi-mode mobile computing devices and peripherals

An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modern PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

Protocol neutral fabric

Methods and apparatus relating to increasing energy efficiency of sensor controllers are described. In an embodiment, logic (e.g., within a sensor controller) performs one or more tasks corresponding to acquisition of data from one or more sensors. The logic performs the one or more tasks to allow a processor core of the sensor controller to enter (or stay in) a low power consumption state during performance of the one or more data acquisition tasks. Other embodiments are also disclosed and claimed.

Techniques for increasing energy efficiency of sensor controllers that receive data from one or more sensors

Systems and methods of managing break events may provide for detecting a first break event from a first event source and detecting a second break event from a second event source. In one example, the event sources can include devices coupled to a platform as well as active applications on the platform. Issuance of the first and second break events to the platform can be coordinated based on at least in part runtime information associated with the platform.

Coordinating device and application break events for platform power saving

Systems and methods may provide for identifying a workload cycle for a computing platform, wherein the workload cycle is to include a busy duration and an idle duration. Additionally, platform energy consumption information may be determined for the workload cycle, and a frequency setting may be selected for the busy duration based at least in part on the platform energy consumption information.

Joint optimization of processor frequencies and system sleep states

Methods and apparatuses for routing voice Internet Protocol (IP) packet to a selected processor are described herein. The methods may include initially receiving at a digital baseband receiver of a device a plurality of IP packets. After receiving the IP packets, the digital baseband receiver may determine whether the IP packets are voice or non-voice IP packets. If the IP packets are determined to be non-voice IP packets, the digital baseband receiver may route the non-voice IP packets to a first processor for processing. On the other hand, if the IP packets are determined to be voice IP packets, the digital baseband receiver may route the voice IP packets to a second processor for processing.

Routing of voice internet protocol packets to a selected processor

Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.

Emulation of an input/output advanced programmable interrupt controller

An embodiment integrates non-PCI compliant devices with PCI compliant operating systems. A fabric system mimics the behavior of PCI. When non-PCI compliant devices do not know how to respond to PCI enumeration, embodiments provide a PCI enumeration reply and thus emulate a reply that would typically come from a PCI compliant device during emulation. Embodiments allow system designers to incorporate non-standard fabric structures with the benefit of still using robust and mature PCI infrastructure found in modem PCI compliant operating systems. More generally, embodiments allow an operating system compliant with a first standard (but not a second standard) to discover and communicate with a device that is non-compliant with the first standard (but possibly is compliant with the second standard). Other embodiments are described herein.

Techniques to provide processor state for implementing a power state transition of a processor. In an embodiment, an operating system executing on a processor detects an opportunity to transition the processor to an idle processor power state. In particular embodiments, the operating system initiates the transition by invoking a task switch, wherein information describing a state of the processor is saved to a task switch segment.

Method, apparatus and system to save processor state for efficient transition between processor power states

A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core.

Method, system and apparatus for low-power storage of processor context information

Growing community of inventors

Morgan Hill, CA, United States of America

Bruce L Fleming