International Business Machines Corporation

Lenovo (singapore) Pte. Ltd.

Bruce James Wilkie

Jorge Enrique Muyshondt

Daniel N De Araujo

John M Dinwiddie, Jr

Gustavo A Suarez

Bobby J Freeman

Gary A Parker

Bhyrav M Mutnury

Moises Cases

Terence K Rodrigues

Lawrence Joseph Grasso

Charles R Dart

Edmund Sutherland Gamble

Gary Anthony Jansma

Robert Joseph Ruckriegel

Gregory Alan Flurry

James O Nicholson

Darryl C Newell

James T Hanna

Karl F Schroeder

Barney Louis Hallman

Pravin S Patel

Justin Potok Bandholz

Nam Huu Pham

Christopher Landon Wood

Howard Victor Mahaney, Jr

Shiva R Dasari

Jerrod Kimmel Buterbaugh

Clifton Ehrich Kerr

Daniel Ernest Hurlimann

Lee Hardy Wilson

George D Kokkosoulis

Mark A Brandyberry

Steven Michael Christensen

Nickolaus J Gruendler

Lonnie J Cannon

Amit Sumanlal Shah

Ross M Fleischman

Thomas J Micallef

Methods, apparatus, and computer program products are disclosed for clock signal synchronization among computers in a network, including designating, as a primary clock signal for all the computers in a network, a clock signal from one of the computers in the network; providing the primary clock signal, simultaneously and in parallel, from the computer whose clock signal is designated as the primary clock signal to all the other computers in the network; and providing the primary clock signal, simultaneously and in parallel, from each computer in the network to all computers in the network through multiplexers and phase locked loops, with the primary clock signal locked in phase across all the computers by a phase locked loop on each computer.

Clock signal synchronization among computers in a network

A data processing assembly includes one or more hosts connected to one or more I/O Expansion Drawers. Assignment state information is stored on the Expansion Drawer to convey the assignment state of Expansion Drawer(s) resources to the hosts. The host retrieves the assignment state and, from it, determines, for each Expansion Buss cable connected to the host, the number of Expansion Cards in the Expansion Drawer to configure. A change in the number of Expansion Cards in the expansion apparatus may necessitate a change in the assignment state, which can be electronically accommodated (as opposed to a manual reconfiguration). Similarly, a failure of an Expansion Buss cable is addressed by electronically reassigning resources to another host or to the same host over a different Expansion Buss cable without the need for further manual intervention. The assembly is capable of verifying correct cable connection between a host and the Expansion Drawer.

Multiple host support for remote expansion apparatus

Methods, apparatus, and products for optimizing delivery of regulated power from a voltage regulator to an electrical component, operation of the voltage regulator controlled by a service processor, the voltage regulator including a number of phases, each phase rated to deliver a different maximum power to the electrical component, where optimizing delivery of regulated power includes determining, by the service processor, the present power requirements of the electrical component, and enabling, by the service processor, one or more phases of the voltage regulator in dependence upon the present power requirements of the electrical component.

Optimizing delivery of regulated power from a voltage regulator to an electrical component

In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem.

Dual-band communication of management traffic in a blade server system

Cables and methods of manufacturing cables for high speed data communications, the cable including: a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the inner conductors and the dielectric layers parallel with and along a longitudinal axis; and folded conductive shield material wrapped in a rotational direction along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps along and about the longitudinal axis, the conductive shield material comprising a first conductive layer and second conductive layer separated by an inner-shield dielectric layer.

Cable for high speed data communications

A method and system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.

Monitoring VRM-induced memory errors

Methods and apparatus are disclosed for handling fatal computer hardware errors on a computer that include halting data processing operations of the computer upon occurrence of a fatal hardware error; signaling by a source chip of a chipset to the programmable logic device the occurrence of a fatal hardware error; signaling by the programmable logic device to an embedded system microcontroller the occurrence of a fatal hardware error; reading by the embedded system microcontroller through at least one sideband bus from registers in chips of the chipset information regarding the cause of the fatal hardware error; and storing by the embedded system microcontroller the information in non-volatile random access memory of the embedded system microcontroller.

Handling fatal computer hardware errors

Embodiments of the invention address deficiencies of the art in respect to power sequencing, and provide a method, system and computer program product for supporting coupling with independent logic circuits. In one embodiment of the invention, a computer system supporting coupling with independent logic circuits may include an independent logic circuit including at least one voltage regulator that regulates voltage to core logic such that voltage is transferred to the core logic upon receiving a first level of voltage. The independent logic circuit may further include an I/O driver that becomes operational upon receiving a highest level of voltage higher than the first level of voltage. The computer system may further include a voltage ramp for transferring voltage to the independent logic circuit at the first level voltage for a predetermined period of time and subsequently at the highest level of voltage.

Controlled power sequencing for independent logic circuits that transfers voltage at a first level for a predetermined period of time and subsequently at a highest level

A cable having an electrically conducting wire with a cross sectional shape defined by a simple closed curve having from three to eight concave portions separated by an equal number of convex portions. The simple closed curve has no point where the radius of curvature is less than one-sixth (&#x2159;) of an overall radius of the wire and no point where adjacent curves or lines intersect at an angle. The alternating concave and convex portions of the cable's cross-sectional shape may have substantially the same curvature. The cross-sectional shape of the cable avoids sharp angles and fight curves.

Conductor cable having a high surface area

A Twinax cable include a first axial cable having an inner diameter portion and an outer diameter portion and including a conductor surrounded by a dielectric material. A second axial cable has an inner diameter portion and an outer diameter portion and including a conductor surrounded by a dielectric material, the second axial cable being arranged such that a portion of the inner diameter thereof contacts the inner diameter portion of the first axial cable. A drain conductor is disposed between at least a portion of the inner diameter portion of the first axial cable and the inner diameter portion of the second axial cable. In addition, the a first foil layer contacts at least a portion of the outer diameter portion of the first axial cable and a second foil layer contacts at least a portion of the outer diameter portion of the second axial cable. An outer foil layer surrounds the first ax cable, the second axial cable, the first foil layer and the second foil layer.

High-speed cable having increased current return uniformity and method of making same

A system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.

A system and method for handling processor internal errors in a data processing system. The data processing system typically includes a set of main microprocessors that have access to a common system memory via a system bus. The system may further include a service processor that is connected to at least one of the main processors. In addition, the system includes internal error handling hardware configured to log and process internal errors generated by one or more of the main processors. The internal error hardware may include error detection logic configured to receive internal error signals from the main processors. In response to receiving one or more IERR signals, the error detection logic is configured to assert and error detected signal that is received by error logging logic. The error logging logic is configured to update one or more error status register when the error detected signal is asserted. When the error logging logic has updated the status registers, is configured to assert an error logging complete signal that is received by processing control logic. The processor control logic is configured to assert one or more processor enable signals based on the state of the error status registers. In addition, upon completion of the error status update by the error logging logic, the status register is configured to assert an error status updated signal that ultimately produces a system reset. By incorporating error logging and handling into dedicated hardware tied directly to the processor internal error signals, the invention provides a low cost, low response latency mechanism for handling processor internal errors in high performance multiprocessor systems.

Processor internal error handling in an SMP server

Growing community of inventors

Georgetown, TX, United States of America

Bruce James Wilkie