Micron Technology Incorporated

Bruce J Ford

Joseph A De La Cerda

Nicolas Soberanes

Benjamin Rivera

Ezra E Hartz

Christopher Scott Moore

Leland R Nevill

Gregory A Barnett

Than Huu Nguyen

Jonathan Scott Parry

Avani F Trivedi

A host can determine whether to train an AI accelerator of a memory sub-system. Responsive to determining to train the AI accelerator, the host can determine a training category corresponding to a memory access request. The host can also provide an indication to the memory sub-system that causes training of the AI accelerator to be performed based on the training category.

Host training indication for memory artificial intelligence

Apparatuses and methods can be related to reducing memory device overhead using artificial intelligence (AI). Reducing overhead can include receiving file metadata of a data file and device metadata of the memory device. Based on the file metadata and the device metadata, a number of indicators can be selected to provide an indication of an expected use of the data file in the memory device. The number of indicators can be provided to the memory device. The data file can be stored with different data files having matching indicators corresponding thereto.

Memory device overhead reduction using artificial intelligence

A processing device coupled to the memory device can be configured to monitor respective raw bit error rates (RBERs) corresponding to a plurality of groups of memory cells of the memory device. The processing device can also be configured to responsive to determining that an RBER corresponding to a particular group of the plurality of groups of memory cells has met a criteria, adjust a read window budget corresponding to the particular group of memory cells.

Raw bit error rate based trim level adjustments for memory

Apparatuses and methods can be related to implementing adjustable data protection schemes using artificial intelligence. Implementing adjustable data protection schemes can include receiving failure data for the plurality of memory devices and receiving an indication of a failure of a stripe of the plurality of memory devices based on the failure data. Based on failure data, and the indication of the failure of the stripe of the plurality of memory devices, a data protection scheme adjustment can be generated for the memory device. The data protection scheme adjustment can be received from the AI accelerator and can be implemented by a plurality of memory devices.

Adjustable data protection scheme using artificial intelligence

Methods, systems, and devices for memory cell access techniques for memory systems are described. A memory system may receive, from a host system, a set of commands to write data to the memory system. The memory system may analyze a set of parameters associated with the set of commands based on receiving the set of commands. The memory system may determine whether to write the data of the set of commands to the memory system using a first mode or a second mode based on analyzing the parameters. The memory system may write the data using the first mode or the second mode based on the determining.

Memory cell access techniques for memory systems

An apparatus can include an array of memory cells and control circuitry coupled to the array of memory cells. The control circuitry can be configured to store a number of trim settings and receive signaling indicative of a use of the array of memory cells. The control circuitry can be configured to determine an adjustment to the number of trim settings based at least in part on the signaling.

Adjustment to trim settings based on a use of a memory device

A method includes determining a quantity of refresh operations performed on a block of a memory device of a memory sub-system and determining a quantity of write operations and a quantity of read operations performed to the block. The method also includes determining the block is read dominant using the quantity of write operations and the quantity of read operations and determining whether the quantity of refresh operations has met a criteria. The method further includes, responsive to determining that the block is read dominant and that the quantity of refresh operations has met the criteria, modifying trim settings used to operate the block of the memory device.

Trim level adjustments for memory based on data use

Apparatuses and methods can be related to performing prediction based garbage collection. Performing prediction based garbage collection can include performing a first instance of garbage collection, of the memory device, using a first circuitry of the controller and generating a prediction using a second circuitry of the controller. A confidence interval can also be generated for the prediction using the second circuitry of the controller. Responsive to determining that the confidence interval is greater than a threshold, a second instance of garbage collection, of the memory device, can be triggered using the first circuitry of the controller where the first instance of garbage collection is triggered before the second instance of garbage collection.

Prediction based garbage collection

Methods, systems, and devices for adjustable media management are described. A media management operation may be performed at a first rate. During the media management operation, invalid data may be moved from a first block of memory cells to a second block of memory cells at the first rate to free space in the first block. Based on one or more conditions of the memory device, the rate that the media management operation is performed may be adjusted to a second rate. For example, the rate may be lowered based on a quantity of access operations performed on the memory device. Invalid data may continue to be moved from the first block of memory cells to the second block of memory cells at the second rate.

Adjustable media management

The present invention is directed to a system comprised of a computer, at least one integrated circuit tester, a communications link enabling communications between the integrated circuit tester and the computer, and a computer-readable medium. The computer-readable medium contains a sequence of instructions that, when executed, create a set of tests for integrated circuit testing. The set of tests may include only those tests that are calculated to be statistically significant. A second set of tests may be created that includes only those tests that are calculated to be statistically insignificant. The computer monitors the test results and moves tests between the two sets to ensure that only statistically significant tests are in the first group and that only statistically insignificant tests are in the second group.

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Meridian, ID, United States of America

Bruce J Ford